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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-08-27 14:38:44 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-08-27 14:38:44 +0000 |
| commit | fdf189ac9709bd4b645f23010689fd4686c37cc8 (patch) | |
| tree | 17cf394dd7b7681f04b29d785631f80f4d027a70 | |
| parent | bf16f1ddc47303bbbf343152997a342c0c4140bc (diff) | |
Transform float scalar_to_vector into subreg accesses.
No idea whether this is profitable or not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80245 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 7 |
2 files changed, 14 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 78f054e62c..91c2f67089 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -78,7 +78,7 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Expand); + setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom); setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand); if (VT.isInteger()) { @@ -2706,6 +2706,12 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { } static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { + EVT VT = Op.getValueType(); + EVT EltVT = VT.getVectorElementType(); + + if (EltVT.isInteger()) + return SDValue(); + return Op; } diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index f17040da9e..dd098b0460 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -1726,6 +1726,13 @@ def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; +def : Pat<(v2f32 (scalar_to_vector SPR:$src)), + (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>; +def : Pat<(v2f64 (scalar_to_vector DPR:$src)), + (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>; +def : Pat<(v4f32 (scalar_to_vector SPR:$src)), + (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>; + // VDUP : Vector Duplicate (from ARM core register to all elements) class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> |