diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-19 18:52:55 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-19 18:52:55 +0000 |
| commit | fabc8ffacb0bceeaad7bbde79b49f8ad7b5666e3 (patch) | |
| tree | e76c47e78ef639974c10c3a86629686f3f9e4158 | |
| parent | 03ba7b9f25b60b1e95caacb34b0a7e8fc05e860e (diff) | |
Put reg classes into namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22926 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPC32RegisterInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPC64RegisterInfo.td | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/PPC32RegisterInfo.td b/lib/Target/PowerPC/PPC32RegisterInfo.td index c725551d7f..a77590277a 100644 --- a/lib/Target/PowerPC/PPC32RegisterInfo.td +++ b/lib/Target/PowerPC/PPC32RegisterInfo.td @@ -15,7 +15,7 @@ include "PowerPCRegisterInfo.td" /// Register classes // Allocate volatiles first // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 -def GPRC : RegisterClass<i32, 32, +def GPRC : RegisterClass<"PPC32", i32, 32, [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R31, R0, R1, LR]> @@ -33,8 +33,8 @@ def GPRC : RegisterClass<i32, 32, }]; } -def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, +def FPRC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; -def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>; +def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>; diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.td b/lib/Target/PowerPC/PPC64RegisterInfo.td index 974ebecb1d..083154814a 100644 --- a/lib/Target/PowerPC/PPC64RegisterInfo.td +++ b/lib/Target/PowerPC/PPC64RegisterInfo.td @@ -15,7 +15,7 @@ include "PowerPCRegisterInfo.td" /// Register classes // Allocate volatiles first // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 -def GPRC : RegisterClass<i64, 64, +def GPRC : RegisterClass<"PPC64", i64, 64, [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R31, R0, R1, LR]> @@ -33,8 +33,8 @@ def GPRC : RegisterClass<i64, 64, }]; } -def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, +def FPRC : RegisterClass<"PPC64", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; -def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>; +def CRRC : RegisterClass<"PPC64", i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>; |