diff options
| author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-01-12 07:22:45 +0000 |
|---|---|---|
| committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-01-12 07:22:45 +0000 |
| commit | f998a7e671e69269697fd8f8803637e843f983d1 (patch) | |
| tree | 1721954227a593531230e03dc6c7456b39e32647 | |
| parent | c43f91fb49b1db8c2fb922f48ee5fb6bb86881e8 (diff) | |
Output mov %REG = 0 instead of xor %REG, %REG, %REG to clear a
register so that LiveVariable analysis is not confused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10773 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 0cd24813e9..745c219c4f 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -1452,7 +1452,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 }; - static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 }; + static const unsigned ClrOpcode[]={ X86::MOVir8, X86::MOVir16, X86::MOVir32 }; static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX }; static const unsigned DivOpcode[][4] = { @@ -1473,8 +1473,8 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); } else { - // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) - BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); + // If unsigned, emit a zeroing instruction... (reg = 0) + BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0); } // Emit the appropriate divide or remainder instruction... diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 0cd24813e9..745c219c4f 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -1452,7 +1452,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX }; static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 }; static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 }; - static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 }; + static const unsigned ClrOpcode[]={ X86::MOVir8, X86::MOVir16, X86::MOVir32 }; static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX }; static const unsigned DivOpcode[][4] = { @@ -1473,8 +1473,8 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); } else { - // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) - BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); + // If unsigned, emit a zeroing instruction... (reg = 0) + BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0); } // Emit the appropriate divide or remainder instruction... |