diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-15 17:17:48 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-15 17:17:48 +0000 |
| commit | f60ceac9cd7230e0d5ff911fced396f6b5d8c815 (patch) | |
| tree | 063b270dcf79f670b7409e2e06be37309dae7f29 | |
| parent | 4cb971ce1c8b254f29365c988b55f6dcfe86d21e (diff) | |
Another revsh pattern. rdar://9609059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/ARM/rev.ll | 13 |
3 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index fbddd12648..2537fc3691 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3029,6 +3029,10 @@ def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)), (shl GPR:$Rm, (i32 8))), i16), (REVSH GPR:$Rm)>; +def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), + (and (srl GPR:$Rm, (i32 8)), 0xFF)), + (REVSH GPR:$Rm)>; + // Need the AddedComplexity or else MOVs + REV would be chosen. let AddedComplexity = 5 in def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 7d49d5da87..53b9cec6ac 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -2604,6 +2604,10 @@ def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)), (shl rGPR:$Rm, (i32 8))), i16), (t2REVSH rGPR:$Rm)>; +def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), + (and (srl rGPR:$Rm, (i32 8)), 0xFF)), + (t2REVSH rGPR:$Rm)>; + def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>; def t2PKHBT : T2ThreeReg< diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll index 4170ff3071..5739086267 100644 --- a/test/CodeGen/ARM/rev.ll +++ b/test/CodeGen/ARM/rev.ll @@ -54,3 +54,16 @@ entry: %conv8 = ashr exact i32 %sext, 16 ret i32 %conv8 } + +; rdar://9609059 +define i32 @test5(i32 %i) nounwind readnone { +entry: +; CHECK: test5 +; CHECK: revsh r0, r0 + %shl = shl i32 %i, 24 + %shr = ashr exact i32 %shl, 16 + %shr23 = lshr i32 %i, 8 + %and = and i32 %shr23, 255 + %or = or i32 %shr, %and + ret i32 %or +} |