Add pseudo-registers and register class for 64-bit integer values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14332 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 62 insertions, 4 deletions

diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 67a67428e9..aa86e4859c 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -131,8 +131,8 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   case Type::FloatTyID:  return &FPRegsInstance;
   case Type::DoubleTyID: return &DFPRegsInstance;
   case Type::LongTyID:
-  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
-  default:              assert(0 && "Invalid type to getClass!");
+  case Type::ULongTyID:  return &LongRegsInstance;
+  default:               assert(0 && "Invalid type to getClass!");
   case Type::BoolTyID:
   case Type::SByteTyID:
   case Type::UByteTyID:
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index d8d130ccf5..d424ebe648 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -16,6 +16,10 @@
 class Ri<bits<5> num> : Register {
   field bits<5> Num = num;
 }
+// Rl - Slots in the integer register file for 64-bit integer values.
+class Rl<bits<5> num> : Register {
+  field bits<5> Num = num;
+}
 // Rf - 32-bit floating-point registers
 class Rf<bits<5> num> : Register {
   field bits<5> Num = num;
@@ -40,6 +44,12 @@ let Namespace = "V8" in {
   def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
   def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
 
+  // Aliases of the Ri registers used to hold 64-bit integer values.
+  def LG2 : Rl< 2>; def LG4 : Rl< 4>; def LG6 : Rl< 6>;
+  def LO0 : Rl< 8>; def LO2 : Rl<10>; def LO4 : Rl<12>;
+  def LL0 : Rl<16>; def LL2 : Rl<18>; def LL4 : Rl<20>; def LL6 : Rl<22>;
+  def LI0 : Rl<24>; def LI2 : Rl<26>; def LI4 : Rl<28>;
+
   // Standard register aliases.
   def SP : Ri<14>;    def FP : Ri<30>;
 
@@ -82,6 +92,9 @@ def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
   }];
 }
 
+def LongRegs : RegisterClass<i64, 8, [LL0, LL2, LL4, LL6, LI0, LI2,
+  LI4, LG2, LG4, LG6, LO0, LO2, LO4]>;
+
 def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
   F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
@@ -107,3 +120,19 @@ def : RegisterAliases<D12, [F24, F25]>;
 def : RegisterAliases<D13, [F26, F27]>;
 def : RegisterAliases<D14, [F28, F29]>;
 def : RegisterAliases<D15, [F30, F31]>;
+
+// Tell the register file generator that the long integer pseudo-registers
+// alias the registers used for single-word integer values.
+def : RegisterAliases<LL0, [L0, L1]>;
+def : RegisterAliases<LL2, [L2, L3]>;
+def : RegisterAliases<LL4, [L4, L5]>;
+def : RegisterAliases<LL6, [L6, L7]>;
+def : RegisterAliases<LI0, [I0, I1]>;
+def : RegisterAliases<LI2, [I2, I3]>;
+def : RegisterAliases<LI4, [I4, I5]>;
+def : RegisterAliases<LG2, [G2, G3]>;
+def : RegisterAliases<LG4, [G4, G5]>;
+def : RegisterAliases<LG6, [G6, G7]>;
+def : RegisterAliases<LO0, [O0, O1]>;
+def : RegisterAliases<LO2, [O2, O3]>;
+def : RegisterAliases<LO4, [O4, O5]>;
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index 67a67428e9..aa86e4859c 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -131,8 +131,8 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   case Type::FloatTyID:  return &FPRegsInstance;
   case Type::DoubleTyID: return &DFPRegsInstance;
   case Type::LongTyID:
-  case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
-  default:              assert(0 && "Invalid type to getClass!");
+  case Type::ULongTyID:  return &LongRegsInstance;
+  default:               assert(0 && "Invalid type to getClass!");
   case Type::BoolTyID:
   case Type::SByteTyID:
   case Type::UByteTyID:
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index d8d130ccf5..d424ebe648 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -16,6 +16,10 @@
 class Ri<bits<5> num> : Register {
   field bits<5> Num = num;
 }
+// Rl - Slots in the integer register file for 64-bit integer values.
+class Rl<bits<5> num> : Register {
+  field bits<5> Num = num;
+}
 // Rf - 32-bit floating-point registers
 class Rf<bits<5> num> : Register {
   field bits<5> Num = num;
@@ -40,6 +44,12 @@ let Namespace = "V8" in {
   def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
   def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
 
+  // Aliases of the Ri registers used to hold 64-bit integer values.
+  def LG2 : Rl< 2>; def LG4 : Rl< 4>; def LG6 : Rl< 6>;
+  def LO0 : Rl< 8>; def LO2 : Rl<10>; def LO4 : Rl<12>;
+  def LL0 : Rl<16>; def LL2 : Rl<18>; def LL4 : Rl<20>; def LL6 : Rl<22>;
+  def LI0 : Rl<24>; def LI2 : Rl<26>; def LI4 : Rl<28>;
+
   // Standard register aliases.
   def SP : Ri<14>;    def FP : Ri<30>;
 
@@ -82,6 +92,9 @@ def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
   }];
 }
 
+def LongRegs : RegisterClass<i64, 8, [LL0, LL2, LL4, LL6, LI0, LI2,
+  LI4, LG2, LG4, LG6, LO0, LO2, LO4]>;
+
 def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
   F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
   F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
@@ -107,3 +120,19 @@ def : RegisterAliases<D12, [F24, F25]>;
 def : RegisterAliases<D13, [F26, F27]>;
 def : RegisterAliases<D14, [F28, F29]>;
 def : RegisterAliases<D15, [F30, F31]>;
+
+// Tell the register file generator that the long integer pseudo-registers
+// alias the registers used for single-word integer values.
+def : RegisterAliases<LL0, [L0, L1]>;
+def : RegisterAliases<LL2, [L2, L3]>;
+def : RegisterAliases<LL4, [L4, L5]>;
+def : RegisterAliases<LL6, [L6, L7]>;
+def : RegisterAliases<LI0, [I0, I1]>;
+def : RegisterAliases<LI2, [I2, I3]>;
+def : RegisterAliases<LI4, [I4, I5]>;
+def : RegisterAliases<LG2, [G2, G3]>;
+def : RegisterAliases<LG4, [G4, G5]>;
+def : RegisterAliases<LG6, [G6, G7]>;
+def : RegisterAliases<LO0, [O0, O1]>;
+def : RegisterAliases<LO2, [O2, O3]>;
+def : RegisterAliases<LO4, [O4, O5]>;