diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2005-02-10 01:52:22 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2005-02-10 01:52:22 +0000 |
| commit | f5024ff76d750ebab692a0b133db5af513dae267 (patch) | |
| tree | 172a331b33dca8c39836d3c7fdea3a2d6bee3ff0 | |
| parent | 27ae027bc71779c0ab195d5af880303257007f0e (diff) | |
* Fix spelling of `volatile'
* Align comments with tablegen elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20103 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.td | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td index 46491c1d7e..3ed2b5539d 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.td +++ b/lib/Target/Alpha/AlphaRegisterInfo.td @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// // +// This file describes the Alpha register set. // //===----------------------------------------------------------------------===// @@ -78,19 +79,18 @@ def F30 : FPR<30, "$f30">; def F31 : FPR<31, "$f31">; /// Register classes def GPRC : RegisterClass<i64, 64, -//Volitle - [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27, -//Non-Volitile + // Volatile + [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, + R23, R24, R25, R27, + // Non-volatile R9, R10, R11, R12, R13, R14, R15, R26, /* R28, */ R29 /* R30, R31*/ ]>; -//R28 is reserved for the assembler + // Note: R28 is reserved for the assembler -//Don't allocate 15, 29, 30, 31 -//Allocation volatiles only for now +// Don't allocate 15, 29, 30, 31 +// Allocation volatiles only for now def FPRC : RegisterClass<f64, 64, [F0, F1, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, - //Saved: + // Saved: F2, F3, F4, F5, F6, F7, F8, F9 ]>; - - |