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| author | Evan Cheng <evan.cheng@apple.com> | 2006-04-14 07:43:12 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-04-14 07:43:12 +0000 |
| commit | f3e1b1d716ccff0ccb387802349c5a813f223241 (patch) | |
| tree | 389f5175e07608fa576384dd89889c1bbc6b3e81 | |
| parent | d9245ca1a1aa96371a2513c91a3e2a1f26b16e22 (diff) | |
Misc. SSE2 intrinsics: clflush, lfench, mfence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27699 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/IntrinsicsX86.td | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 13 |
2 files changed, 17 insertions, 2 deletions
diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index 9b0a9827ff..d9ea2b850b 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -455,6 +455,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">, Intrinsic<[llvm_void_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>; + def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">, + Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>; + def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">, + Intrinsic<[llvm_void_ty], [IntrWriteMem]>; + def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">, + Intrinsic<[llvm_void_ty], [IntrWriteMem]>; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index d524eb7814..2e190f4f6d 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2002,12 +2002,21 @@ def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src), [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>, TB, Requires<[HasSSE2]>; -// Store fence +// Flush cache +def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src), + "clflush $src", [(int_x86_sse2_clflush addr:$src)]>, + TB, Requires<[HasSSE2]>; + +// Load, store, and memory fence def SFENCE : I<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>; +def LFENCE : I<0xAE, MRM5m, (ops), + "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>; +def MFENCE : I<0xAE, MRM6m, (ops), + "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>; // MXCSR register -def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src), +def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src), "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>; def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst), |