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| author | Jeff Cohen <jeffc@jolt-lang.org> | 2006-02-04 16:20:31 +0000 |
|---|---|---|
| committer | Jeff Cohen <jeffc@jolt-lang.org> | 2006-02-04 16:20:31 +0000 |
| commit | f3afef3b3a9d7c4ca69d4b0306a684a61e1e50d5 (patch) | |
| tree | 35e232a75123c3149caa87d8cc462aacbec15514 | |
| parent | 0a70f219f45077dfaa7e37ad1ed6f760f1f7a1e8 (diff) | |
Fix VC++ warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25975 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 58344872a5..1574870569 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -301,7 +301,6 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) { // Add all of the operand registers to the instruction. for (unsigned i = 2; i != NumOps; i += 2) { unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue(); - MachineOperand::UseType UseTy; switch (Flags) { default: assert(0 && "Bad flags!"); case 1: { // Use of register. |