diff options
| author | Daniel Dunbar <daniel@zuster.org> | 2010-03-09 22:50:46 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2010-03-09 22:50:46 +0000 |
| commit | f291be3159530fdca2fd5e726ec2bd3100f38e55 (patch) | |
| tree | 09d997160df421b1240ff87ff76ecfde1e9de26e | |
| parent | 1e8ee89c213704c398d8a7ea2567a30b0f75eb5f (diff) | |
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98098 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 20 | ||||
| -rw-r--r-- | test/MC/AsmParser/X86/x86_32-new-encoder.s | 3 |
2 files changed, 14 insertions, 9 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 4b43e658e7..071c5aa31a 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2647,6 +2647,17 @@ def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), } // end isConvertibleToThreeAddress } // end isCommutable +// These are alternate spellings for use by the disassembler, we mark them as +// code gen only to ensure they aren't matched by the assembler. +let isCodeGenOnly = 1 in { + def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), + "add{b}\t{$src2, $dst|$dst, $src2}", []>; + def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), + "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; + def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), + "add{l}\t{$src2, $dst|$dst, $src2}", []>; +} + // Register-Memory Addition def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2), @@ -2664,15 +2675,6 @@ def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), (implicit EFLAGS)]>; -// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, -// ADD16rr, and ADD32rr), but differently encoded. -def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), - "add{b}\t{$src2, $dst|$dst, $src2}", []>; -def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), - "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; -def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), - "add{l}\t{$src2, $dst|$dst, $src2}", []>; - // Register-Integer Addition def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), "add{b}\t{$src2, $dst|$dst, $src2}", diff --git a/test/MC/AsmParser/X86/x86_32-new-encoder.s b/test/MC/AsmParser/X86/x86_32-new-encoder.s index 63ae9d1bbd..d4e3be4bd2 100644 --- a/test/MC/AsmParser/X86/x86_32-new-encoder.s +++ b/test/MC/AsmParser/X86/x86_32-new-encoder.s @@ -44,3 +44,6 @@ rdtscp // CHECK: cmpl %eax, %ebx # encoding: [0x39,0xc3] cmpl %eax, %ebx + +// CHECK: addw %ax, %ax # encoding: [0x66,0x01,0xc0] + addw %ax, %ax |