diff options
| author | Andrew Trick <atrick@apple.com> | 2012-08-29 01:58:55 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-08-29 01:58:55 +0000 |
| commit | f26e43df26bb7b0c7bf4853477e36611e2c90dea (patch) | |
| tree | 6880b6ee11c66eed25d602b29f64239fa811f7eb | |
| parent | d79dedd458c1de07fbc568ea8c3b4194e94df48e (diff) | |
Fix ARM vector copies of overlapping register tuples.
I have tested the fix, but have not been successfull in generating
a robust unit test. This can only be exposed through particular
register assignments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162821 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 5191c3eabe..f3c9cf4e43 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -710,10 +710,23 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI = &getRegisterInfo(); MachineInstrBuilder Mov; + + // Copy register tuples backward when the first Dest reg overlaps with SrcReg. + if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { + BeginIdx = BeginIdx + ((SubRegs-1)*Spacing); + Spacing = -Spacing; + } +#ifndef NDEBUG + SmallSet<unsigned, 4> DstRegs; +#endif for (unsigned i = 0; i != SubRegs; ++i) { unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); assert(Dst && Src && "Bad sub-register"); +#ifndef NDEBUG + DstRegs.insert(Dst); + assert(!DstRegs.count(Src) && "destructive vector copy"); +#endif Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) .addReg(Src); // VORR takes two source operands. |