diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-09 22:12:36 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-09 22:12:36 +0000 |
| commit | ee899e6bfc854adefdbfd6631e206d18fd43ab81 (patch) | |
| tree | 4ac0dcf07a810eefadd1598d56ac877927293919 | |
| parent | 5fb0deb43a3d59a5b2cdee2a51b20ee84babe607 (diff) | |
(X & Y) & C == 0 if either X&C or Y&C are zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23678 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 8 |
2 files changed, 12 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e4aa773249..069a8f9176 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -176,10 +176,15 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::AND: + // If either of the operands has zero bits, the result will too. + if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || + MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) + return true; + // (X & C1) & C2 == 0 iff C1 & C2 == 0. if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); - // FALL THROUGH + return false; case ISD::OR: case ISD::XOR: return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 9a69fdc5fc..b0206a9dcb 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -608,11 +608,15 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::AND: + // If either of the operands has zero bits, the result will too. + if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || + MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) + return true; + // (X & C1) & C2 == 0 iff C1 & C2 == 0. if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); - - // FALL THROUGH + return false; case ISD::OR: case ISD::XOR: return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && |