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authorEvan Cheng <evan.cheng@apple.com>2008-11-19 23:21:11 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-11-19 23:21:11 +0000
commiteda60a8364889a336339571fa4810e439ce895f6 (patch)
treeea8f037a11128f9cf5e9b7b6f950f51033bd9494
parent343f0c046702831a4a6aec951b6a297a23241a55 (diff)
Eliminate a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59677 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86CodeEmitter.cpp10
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 828d1ad651..033d3b61e3 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -516,10 +516,12 @@ void Emitter::emitInstruction(const MachineInstr &MI,
assert(0 && "psuedo instructions should be removed before code emission");
break;
case TargetInstrInfo::INLINEASM: {
- const char* Value = MI.getOperand(0).getSymbolName();
- /* We allow inline assembler nodes with empty bodies - they can
- implicitly define registers, which is ok for JIT. */
- assert((Value[0] == 0) && "JIT does not support inline asm!\n");
+ // We allow inline assembler nodes with empty bodies - they can
+ // implicitly define registers, which is ok for JIT.
+ if (MI.getOperand(0).getSymbolName()[0]) {
+ assert(0 && "JIT does not support inline asm!\n");
+ abort();
+ }
break;
}
case TargetInstrInfo::DBG_LABEL: