Great renaming: Sparc --> SparcV9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8

34 files changed, 375 insertions, 375 deletions

diff --git a/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp b/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
index 40facf3fd9..0e14580386 100644
--- a/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
+++ b/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
@@ -1,4 +1,4 @@
-//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to Sparc .s File --------==//
+//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to SparcV9 .s File --------==//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -13,7 +13,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
 #include "llvm/Pass.h"
 #include "llvm/Bytecode/Writer.h"
 #include <iostream>
@@ -86,13 +86,13 @@ namespace {
 	<< "\n";
   }
 
-  // SparcBytecodeWriter - Write bytecode out to a stream that is sparc'ified
-  class SparcBytecodeWriter : public Pass {
+  // SparcV9BytecodeWriter - Write bytecode out to a stream that is sparc'ified
+  class SparcV9BytecodeWriter : public Pass {
     std::ostream &Out;
   public:
-    SparcBytecodeWriter(std::ostream &out) : Out(out) {}
+    SparcV9BytecodeWriter(std::ostream &out) : Out(out) {}
 
-    const char *getPassName() const { return "Emit Bytecode to Sparc Assembly";}
+    const char *getPassName() const { return "Emit Bytecode to SparcV9 Assembly";}
     
     virtual bool run(Module &M) {
       // Write an object containing the bytecode to the SPARC assembly stream
@@ -113,7 +113,7 @@ namespace {
 }  // end anonymous namespace
 
 Pass *createBytecodeAsmPrinterPass(std::ostream &Out) {
-  return new SparcBytecodeWriter(Out);
+  return new SparcV9BytecodeWriter(Out);
 }
 
 } // End llvm namespace
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index a7923862cf..46bc81f602 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -23,7 +23,7 @@
 #include "llvm/Constants.h"
 #include "llvm/BasicBlock.h"
 #include "llvm/DerivedTypes.h"
-#include "../SparcInstrSelectionSupport.h"
+#include "../SparcV9InstrSelectionSupport.h"
 
 namespace llvm {
 
diff --git a/lib/Target/SparcV9/InstrSelection/Makefile b/lib/Target/SparcV9/InstrSelection/Makefile
index ac44f3a724..7e807cec42 100644
--- a/lib/Target/SparcV9/InstrSelection/Makefile
+++ b/lib/Target/SparcV9/InstrSelection/Makefile
@@ -9,6 +9,6 @@
 
 LEVEL = ../../../..
 DIRS  = 
-LIBRARYNAME = select
+LIBRARYNAME = sparcv9select
 
 include $(LEVEL)/Makefile.common
diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
index 9f9aaf5dde..fd8c662cc5 100644
--- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
+++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
@@ -17,7 +17,7 @@
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Support/CFG.h"
 #include "Support/SetOperations.h"
-#include "../SparcInternals.h"
+#include "../SparcV9Internals.h"
 
 namespace llvm {
 
diff --git a/lib/Target/SparcV9/LiveVar/Makefile b/lib/Target/SparcV9/LiveVar/Makefile
index 90a664e56c..6973f63aa5 100644
--- a/lib/Target/SparcV9/LiveVar/Makefile
+++ b/lib/Target/SparcV9/LiveVar/Makefile
@@ -8,7 +8,7 @@
 ##===----------------------------------------------------------------------===##
 
 LEVEL = ../../../..
-LIBRARYNAME = livevar
+LIBRARYNAME = sparcv9livevar
 
 include $(LEVEL)/Makefile.common
 
diff --git a/lib/Target/SparcV9/Makefile b/lib/Target/SparcV9/Makefile
index 619c9d02e7..3c028f1632 100644
--- a/lib/Target/SparcV9/Makefile
+++ b/lib/Target/SparcV9/Makefile
@@ -1,4 +1,4 @@
-##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
+##===- lib/Target/SparcV9/Makefile ---------------------------*- Makefile -*-===##
 # 
 #                     The LLVM Compiler Infrastructure
 #
@@ -7,10 +7,10 @@
 # 
 ##===----------------------------------------------------------------------===##
 LEVEL = ../../..
-LIBRARYNAME = sparc
+LIBRARYNAME = sparcv9
 DIRS = InstrSelection RegAlloc LiveVar
 
-ExtraSource = Sparc.burm.cpp 
+ExtraSource = SparcV9.burm.cpp 
 
 include $(LEVEL)/Makefile.common
 
@@ -20,26 +20,26 @@ else
   DEBUG_FLAG = -D_DEBUG
 endif
 
-Sparc.burg.in1 : $(SourceDir)/Sparc.burg.in
+SparcV9.burg.in1 : $(SourceDir)/SparcV9.burg.in
 	$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/Ydefine/#define/' > $@
 
-Sparc.burm : Sparc.burg.in1
+SparcV9.burm : SparcV9.burg.in1
 	$(CXX) -E -I$(LLVM_SRC_ROOT)/include $(DEBUG_FLAG) -x c++ $< | $(SED) '/^#/d' | $(SED) 's/^Xinclude/#include/' | $(SED) 's/^Xdefine/#define/' > $@
 
-Sparc.burm.cpp: Sparc.burm
+SparcV9.burm.cpp: SparcV9.burm
 	@echo "Burging `basename $<`"
 	$(RunBurg) $< -o $@
 
-$(BUILD_OBJ_DIR)/Debug/Sparc.burm.lo: Sparc.burm.cpp
+$(BUILD_OBJ_DIR)/Debug/SparcV9.burm.lo: SparcV9.burm.cpp
 	$(CompileG) $< -o $@
 
-$(BUILD_OBJ_DIR)/Release/Sparc.burm.lo: Sparc.burm.cpp
+$(BUILD_OBJ_DIR)/Release/SparcV9.burm.lo: SparcV9.burm.cpp
 	$(CompileO) $< -o $@
 
-$(BUILD_OBJ_DIR)/Profile/Sparc.burm.lo: Sparc.burm.cpp
+$(BUILD_OBJ_DIR)/Profile/SparcV9.burm.lo: SparcV9.burm.cpp
 	$(CompileP) $< -o $@
 
-$(BUILD_OBJ_DIR)/Depend/Sparc.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
+$(BUILD_OBJ_DIR)/Depend/SparcV9.burm.d: $(BUILD_OBJ_DIR)/Depend/.dir
 	touch $@
 
 TARGET_NAME := SparcV9
@@ -56,5 +56,5 @@ $(TARGET_NAME)CodeEmitter.inc:: $(SourceDir)/$(TARGET_NAME).td $(TABLEGEN_FILES)
 	$(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
 
 clean::
-	$(RM) -f $(TARGET_NAME)CodeEmitter.inc Sparc.burg.in1 Sparc.burm Sparc.burm.cpp
+	$(RM) -f $(TARGET_NAME)CodeEmitter.inc SparcV9.burg.in1 SparcV9.burm SparcV9.burm.cpp
 
diff --git a/lib/Target/SparcV9/MappingInfo.h b/lib/Target/SparcV9/MappingInfo.h
index 6af116a6da..351d5f87a9 100644
--- a/lib/Target/SparcV9/MappingInfo.h
+++ b/lib/Target/SparcV9/MappingInfo.h
@@ -1,4 +1,4 @@
-//===- lib/Target/Sparc/MappingInfo.h ---------------------------*- C++ -*-===//
+//===- lib/Target/SparcV9/MappingInfo.h ---------------------------*- C++ -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
diff --git a/lib/Target/SparcV9/RegAlloc/Makefile b/lib/Target/SparcV9/RegAlloc/Makefile
index 374c70f08a..76f35a8a8c 100644
--- a/lib/Target/SparcV9/RegAlloc/Makefile
+++ b/lib/Target/SparcV9/RegAlloc/Makefile
@@ -10,7 +10,7 @@ LEVEL = ../../../..
 
 DIRS  = 
 
-LIBRARYNAME = regalloc
+LIBRARYNAME = sparcv9regalloc
 
 BUILD_ARCHIVE = 1
 
diff --git a/lib/Target/SparcV9/SparcV9.burg.in b/lib/Target/SparcV9/SparcV9.burg.in
index 38dc2439ce..b466b1f376 100644
--- a/lib/Target/SparcV9/SparcV9.burg.in
+++ b/lib/Target/SparcV9/SparcV9.burg.in
@@ -46,7 +46,7 @@ Xdefine PANIC		printf
 %term Or=OrOPCODE
 %term Xor=XorOPCODE
                 /* Use the next 4 to distinguish bitwise operators from
-                 * logical operators.  This is no longer used for Sparc,
+                 * logical operators.  This is no longer used for SparcV9,
                  * but may be useful for other target machines.
                  * The last one is the bitwise Not(val) == XOR val, 11..1.
                  * Note that it is also a binary operator, not unary.
diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td
index 4cb00102e2..f20b57d909 100644
--- a/lib/Target/SparcV9/SparcV9.td
+++ b/lib/Target/SparcV9/SparcV9.td
@@ -1,4 +1,4 @@
-//===- SparcV9.td - Target Description for Sparc V9 Target ----------------===//
+//===- SparcV9.td - Target Description for SparcV9 V9 Target ----------------===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -19,7 +19,7 @@ include "SparcV9_Reg.td"
 // Instructions
 //===----------------------------------------------------------------------===//
 
-class InstV9 : Instruction {          // Sparc instruction baseline
+class InstV9 : Instruction {          // SparcV9 instruction baseline
   field bits<32> Inst;
 
   let Namespace = "V9";
@@ -27,7 +27,7 @@ class InstV9 : Instruction {          // Sparc instruction baseline
   bits<2> op;
   let Inst{31-30} = op;               // Top two bits are the 'op' field
 
-  // Bit attributes specific to Sparc instructions
+  // Bit attributes specific to SparcV9 instructions
   bit isPasi       = 0; // Does this instruction affect an alternate addr space?
   bit isDeprecated = 0; // Is this instruction deprecated?
   bit isPrivileged = 0; // Is this a privileged instruction?
@@ -62,7 +62,7 @@ let op2 = 0b011 in {
 }
 
 // Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
-// The following deprecated instructions don't seem to play nice on Sparc
+// The following deprecated instructions don't seem to play nice on SparcV9
 /*
 let isDeprecated = 1 in {
   let op2 = 0b110 in {
@@ -107,7 +107,7 @@ let op2 = 0b101 in {
 }
 
 // Section A.5: Branch on FP condition codes with prediction - p143
-// Not used in the Sparc backend (directly)
+// Not used in the SparcV9 backend (directly)
 /*
 let op2 = 0b101 in {
   def FBPA     : F2_3<0b1000, "fba">;              // Branch always
@@ -176,7 +176,7 @@ let op2 = 0b001 in {
 }
 
 // Section A.7: Branch on integer condition codes with prediction - p148
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
 /*
 let op2 = 0b001 in {
   def BPA     : F2_3<0b1000, "bpa">;              // Branch always
@@ -212,7 +212,7 @@ def CALL : InstV9 {
 
 
 // Section A.10: Divide (64-bit / 32-bit) - p178
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
 /*
 let isDeprecated = 1 in {
   def UDIVr   : F3_1<2, 0b001110, "udiv">;        // udiv r, r, r
@@ -227,7 +227,7 @@ let isDeprecated = 1 in {
 */
 
 // Section A.11: DONE and RETRY - p181
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
 /*
 let isPrivileged = 1 in {
   def DONE    : F3_18<0, "done">;                 // done
@@ -247,7 +247,7 @@ def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">;    // fsubq frs1, frs2, frd
 def FCMPS  : F3_15<2, 0b110101, 0b001010001, "fcmps">;   // fcmps  %fcc, r1, r2
 def FCMPD  : F3_15<2, 0b110101, 0b001010010, "fcmpd">;   // fcmpd  %fcc, r1, r2
 def FCMPQ  : F3_15<2, 0b110101, 0b001010011, "fcmpq">;   // fcmpq  %fcc, r1, r2
-// Currently unused in the Sparc backend
+// Currently unused in the SparcV9 backend
 /*
 def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">;  // fcmpes %fcc, r1, r2
 def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">;  // fcmped %fcc, r1, r2
@@ -317,7 +317,7 @@ def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">;  // fsqrts r, r
 // Not currently used
 
 // Section A.24: Jump and Link - p172
-// Mimicking the Sparc's instr def...
+// Mimicking the SparcV9's instr def...
 def JMPLCALLr : F3_1<2, 0b111000, "jmpl">;              // jmpl [rs1+rs2], rd
 def JMPLCALLi : F3_2<2, 0b111000, "jmpl">;              // jmpl [rs1+imm], rd
 def JMPLRETr  : F3_1<2, 0b111000, "jmpl">;              // jmpl [rs1+rs2], rd
@@ -393,7 +393,7 @@ def XNORccr : F3_1<2, 0b010111, "xnorcc">;       // xnorcc rs1, rs2, rd
 def XNORcci : F3_2<2, 0b010111, "xnorcc">;       // xnorcc rs1, imm, rd
 
 // Section A.32: Memory Barrier - p186
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
 // ======================= Single Floating Point ======================
@@ -622,7 +622,7 @@ def UDIVXr : F3_1<2, 0b001101, "udivx">;       // udivx  r, r, r
 def UDIVXi : F3_2<2, 0b001101, "udivx">;       // udivx  r, i, r
 
 // Section A.38: Multiply (32-bit) - p200
-// Not used in the Sparc backend
+// Not used in the SparcV9 backend
 /*
 let Inst{13} = 0 in {
   def UMULr   : F3_1<2, 0b001010, "umul">;        // umul   r, r, r
@@ -639,7 +639,7 @@ let Inst{13} = 1 in {
 */
 
 // Section A.39: Multiply Step - p202
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.40: No operation - p204
 // NOP is really a pseudo-instruction (special case of SETHI)
@@ -652,13 +652,13 @@ let op2 = 0b100 in {
 }
 
 // Section A.41: Population Count - p205
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.42: Prefetch Data - p206
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.43: Read Privileged Register - p211
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.44: Read State Register
 // The only instr from this section currently used is RDCCR
@@ -679,7 +679,7 @@ def RESTOREr : F3_1<2, 0b111101, "restore">;    // restore r, r, r
 def RESTOREi : F3_2<2, 0b111101, "restore">;    // restore r, i, r
 
 // Section A.47: SAVED and RESTORED - p219
-// Not currently used in Sparc backend
+// Not currently used in SparcV9 backend
 
 // Section A.48: SETHI - p220
 let op2 = 0b100 in {
@@ -687,7 +687,7 @@ let op2 = 0b100 in {
 }
 
 // Section A.49: Shift - p221
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 /*
  uses 5 least significant bits of rs2
 let x = 0 in {
@@ -720,10 +720,10 @@ def SRLXi6 : F3_13<2, 0b100110, "srlx">;                 // srlx r, shcnt64, r
 def SRAXi6 : F3_13<2, 0b100111, "srax">;                 // srax r, shcnt64, r
 
 // Section A.50: Sofware-Initiated Reset - p223
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.51: Store Barrier - p224
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.52: Store Floating-point - p225
 // Store instructions all want their rd register first
@@ -732,7 +732,7 @@ def STFi  : F3_2rd<3, 0b100100, "st">;                      // st r, [r+i]
 def STDFr : F3_1rd<3, 0b100111, "std">;                     // std r, [r+r]
 def STDFi : F3_2rd<3, 0b100111, "std">;                     // std r, [r+i]
 
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 /*
 def STQFr : F3_1rd<3, 0b100110, "stq">;                     // stq r, [r+r]
 def STQFi : F3_2rd<3, 0b100110, "stq">;                     // stq r, [r+i]
@@ -740,7 +740,7 @@ def STQFi : F3_2rd<3, 0b100110, "stq">;                     // stq r, [r+i]
 
 // FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
 // while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
-// These are being disabled because they aren't used in the Sparc backend.
+// These are being disabled because they aren't used in the SparcV9 backend.
 /*
 let isDeprecated = 1 in {
   def STFSRr : F3_1<3, 0b100101, "st">;                   // st  %fsr, [r+r]
@@ -751,7 +751,7 @@ def STXFSRr : F3_1<3, 0b100101, "stx">;                   // stx %fsr, [r+r]
 def STXFSRi : F3_2<3, 0b100101, "stx">;                   // stx %fsr, [r+i]
 
 // Section A.53: Store Floating-Point into Alternate Space - p227
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.54: Store Integer - p229
 // Store instructions all want their rd register first
@@ -765,7 +765,7 @@ def STXr : F3_1rd<3, 0b001110, "stx">;                     // stx r, [r+r]
 def STXi : F3_2rd<3, 0b001110, "stx">;                     // stx r, [r+i]
 
 // Section A.55: Store Integer into Alternate Space - p231
-// Not currently used in the Sparc backend
+// Not currently used in the SparcV9 backend
 
 // Section A.56: Subtract - p233
 def SUBr    : F3_1<2, 0b000100, "sub">;                   // sub r, r, r
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 40aa81cab0..146f11c899 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- EmitAssembly.cpp - Emit Sparc Specific .s File ---------------------==//
+//===-- EmitAssembly.cpp - Emit SparcV9 Specific .s File ---------------------==//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -30,7 +30,7 @@
 #include "llvm/Support/Mangler.h"
 #include "Support/StringExtras.h"
 #include "Support/Statistic.h"
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
 #include <string>
 using namespace llvm;
 
@@ -251,7 +251,7 @@ namespace {
     }
 
     // getID Wrappers - Ensure consistent usage
-    // Symbol names in Sparc assembly language have these rules:
+    // Symbol names in SparcV9 assembly language have these rules:
     // (a) Must match { letter | _ | . | $ } { letter | _ | . | $ | digit }*
     // (b) A name beginning in "." is treated as a local name.
     std::string getID(const Function *F) {
@@ -504,19 +504,19 @@ std::string AsmPrinter::valToExprString(const Value* V,
 
 
 //===----------------------------------------------------------------------===//
-//   SparcAsmPrinter Code
+//   SparcV9AsmPrinter Code
 //===----------------------------------------------------------------------===//
 
 namespace {
 
-  struct SparcAsmPrinter : public FunctionPass, public AsmPrinter {
-    inline SparcAsmPrinter(std::ostream &os, const TargetMachine &t)
+  struct SparcV9AsmPrinter : public FunctionPass, public AsmPrinter {
+    inline SparcV9AsmPrinter(std::ostream &os, const TargetMachine &t)
       : AsmPrinter(os, t) {}
 
     const Function *currFunction;
 
     const char *getPassName() const {
-      return "Output Sparc Assembly for Functions";
+      return "Output SparcV9 Assembly for Functions";
     }
 
     virtual bool doInitialization(Module &M) {
@@ -565,7 +565,7 @@ namespace {
 } // End anonymous namespace
 
 inline bool
-SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
+SparcV9AsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
                                        unsigned int opNum) {
   switch (MI->getOpcode()) {
   case V9::JMPLCALLr:
@@ -579,7 +579,7 @@ SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
 }
 
 inline bool
-SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
+SparcV9AsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
                                        unsigned int opNum) {
   if (Target.getInstrInfo().isLoad(MI->getOpcode()))
     return (opNum == 0);
@@ -596,7 +596,7 @@ SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
   printOneOperand(mop2, opCode);
 
 unsigned int
-SparcAsmPrinter::printOperands(const MachineInstr *MI,
+SparcV9AsmPrinter::printOperands(const MachineInstr *MI,
                                unsigned int opNum)
 {
   const MachineOperand& mop = MI->getOperand(opNum);
@@ -616,7 +616,7 @@ SparcAsmPrinter::printOperands(const MachineInstr *MI,
 }
 
 void
-SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
+SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop,
                                  MachineOpCode opCode)
 {
   bool needBitsFlag = true;
@@ -659,7 +659,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
     case MachineOperand::MO_PCRelativeDisp:
       {
         const Value *Val = mop.getVRegValue();
-        assert(Val && "\tNULL Value in SparcAsmPrinter");
+        assert(Val && "\tNULL Value in SparcV9AsmPrinter");
         
         if (const BasicBlock *BB = dyn_cast<BasicBlock>(Val))
           toAsm << getID(BB);
@@ -670,7 +670,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
         else if (const Constant *CV = dyn_cast<Constant>(Val))
           toAsm << getID(CV);
         else
-          assert(0 && "Unrecognized value in SparcAsmPrinter");
+          assert(0 && "Unrecognized value in SparcV9AsmPrinter");
         break;
       }
     
@@ -691,7 +691,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
     toAsm << ")";
 }
 
-void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
+void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) {
   unsigned Opcode = MI->getOpcode();
 
   if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
@@ -715,7 +715,7 @@ void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
   ++EmittedInsts;
 }
 
-void SparcAsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
+void SparcV9AsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
   // Emit a label for the basic block
   toAsm << getID(MBB.getBasicBlock()) << ":\n";
 
@@ -726,7 +726,7 @@ void SparcAsmPrinter::emitBasicBlock(const MachineBasicBlock &MBB) {
   toAsm << "\n";  // Separate BB's with newlines
 }
 
-void SparcAsmPrinter::emitFunction(const Function &F) {
+void SparcV9AsmPrinter::emitFunction(const Function &F) {
   std::string methName = getID(&F);
   toAsm << "!****** Outputing Function: " << methName << " ******\n";
 
@@ -760,7 +760,7 @@ void SparcAsmPrinter::emitFunction(const Function &F) {
   toAsm << "\n\n";
 }
 
-void SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
+void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
   if (GV->hasExternalLinkage())
     toAsm << "\t.global\t" << getID(GV) << "\n";
   
@@ -776,7 +776,7 @@ void SparcAsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
   }
 }
 
-void SparcAsmPrinter::emitGlobals(const Module &M) {
+void SparcV9AsmPrinter::emitGlobals(const Module &M) {
   // Output global variables...
   for (Module::const_giterator GI = M.gbegin(), GE = M.gend(); GI != GE; ++GI)
     if (! GI->isExternal()) {
@@ -796,5 +796,5 @@ void SparcAsmPrinter::emitGlobals(const Module &M) {
 
 FunctionPass *llvm::createAsmPrinterPass(std::ostream &Out,
                                          const TargetMachine &TM) {
-  return new SparcAsmPrinter(Out, TM);
+  return new SparcV9AsmPrinter(Out, TM);
 }
diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index f2368d654b..8f8946e0c2 100644
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -34,9 +34,9 @@
 #include "Support/Debug.h"
 #include "Support/hash_set"
 #include "Support/Statistic.h"
-#include "SparcInternals.h"
-#include "SparcTargetMachine.h"
-#include "SparcRegInfo.h"
+#include "SparcV9Internals.h"
+#include "SparcV9TargetMachine.h"
+#include "SparcV9RegInfo.h"
 #include "SparcV9CodeEmitter.h"
 #include "Config/alloca.h"
 
@@ -48,12 +48,12 @@ namespace {
   Statistic<> CallbackCalls("callback", "Number CompilationCallback() calls");
 }
 
-bool SparcTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
                                                     MachineCodeEmitter &MCE) {
   MachineCodeEmitter *M = &MCE;
   DEBUG(M = MachineCodeEmitter::createFilePrinterEmitter(MCE));
   PM.add(new SparcV9CodeEmitter(*this, *M));
-  PM.add(createSparcMachineCodeDestructionPass()); //Free stuff no longer needed
+  PM.add(createSparcV9MachineCodeDestructionPass()); //Free stuff no longer needed
   return false;
 }
 
@@ -179,8 +179,8 @@ void JITResolver::insertJumpAtAddr(int64_t JumpTarget, uint64_t &Addr) {
 
 void JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
   static const unsigned 
-    o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
-    g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
+    o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0,
+    g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
 
   MachineInstr* BinaryCode[] = {
     //
@@ -362,7 +362,7 @@ void JITResolver::CompilationCallback() {
   // Rewrite the call target so that we don't fault every time we execute it.
   //
 
-  static const unsigned o6 = SparcIntRegClass::o6;
+  static const unsigned o6 = SparcV9IntRegClass::o6;
 
   // Subtract enough to overwrite up to the 'save' instruction
   // This depends on whether we made a short call (1 instruction) or the
@@ -418,7 +418,7 @@ uint64_t JITResolver::emitStubForFunction(Function *F) {
   DEBUG(std::cerr << "Emitting stub at addr: 0x" 
                   << std::hex << MCE.getCurrentPCValue() << "\n");
 
-  unsigned o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0;
+  unsigned o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0;
 
   // restore %g0, 0, %g0
   MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
@@ -485,8 +485,8 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
   fakeReg = RI.getClassRegNum(fakeReg, regClass);
 
   switch (regClass) {
-  case SparcRegInfo::IntRegClassID: {
-    // Sparc manual, p31
+  case SparcV9RegInfo::IntRegClassID: {
+    // SparcV9 manual, p31
     static const unsigned IntRegMap[] = {
       // "o0", "o1", "o2", "o3", "o4", "o5",       "o7",
       8, 9, 10, 11, 12, 13, 15,
@@ -503,14 +503,14 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
     return IntRegMap[fakeReg];
     break;
   }
-  case SparcRegInfo::FloatRegClassID: {
+  case SparcV9RegInfo::FloatRegClassID: {
     DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
-    if (regType == SparcRegInfo::FPSingleRegType) {
+    if (regType == SparcV9RegInfo::FPSingleRegType) {
       // only numbered 0-31, hence can already fit into 5 bits (and 6)
       DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
-    } else if (regType == SparcRegInfo::FPDoubleRegType) {
+    } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
       // FIXME: This assumes that we only have 5-bit register fields!
-      // From Sparc Manual, page 40.
+      // From SparcV9 Manual, page 40.
       // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
       fakeReg |= (fakeReg >> 5) & 1;
       fakeReg &= 0x1f;
@@ -518,7 +518,7 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
     }
     return fakeReg;
   }
-  case SparcRegInfo::IntCCRegClassID: {
+  case SparcV9RegInfo::IntCCRegClassID: {
     /*                                   xcc, icc, ccr */
     static const unsigned IntCCReg[] = {  6,   4,   2 };
     
@@ -527,7 +527,7 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
     DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
     return IntCCReg[fakeReg];
   }
-  case SparcRegInfo::FloatCCRegClassID: {
+  case SparcV9RegInfo::FloatCCRegClassID: {
     /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
     DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
     return fakeReg;
@@ -542,9 +542,9 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
 // WARNING: if the call used the delay slot to do meaningful work, that's not
 // being accounted for, and the behavior will be incorrect!!
 inline void SparcV9Co