Refactor X87 instructions. As a side effect, all

their names are changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37876 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 377 insertions, 553 deletions

diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index bc6b4c4d1e..fdd8781d84 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -121,7 +121,7 @@ namespace {
         std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
 
         // Emit an fxch to update the runtime processors version of the state
-        BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg);
+        BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
         NumFXCH++;
       }
     }
@@ -130,7 +130,7 @@ namespace {
       unsigned STReg = getSTReg(RegNo);
       pushReg(AsReg);   // New register on top of stack
 
-      BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg);
+      BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
     }
 
     // popStackAfter - Pop the current value off of the top of the FP stack
@@ -324,101 +324,101 @@ static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
 // concrete X86 instruction which uses the register stack.
 //
 static const TableEntry OpcodeTable[] = {
-  { X86::FpABS32     , X86::FABS     },
-  { X86::FpABS64     , X86::FABS     },
-  { X86::FpADD32m    , X86::FADD32m  },
-  { X86::FpADD64m    , X86::FADD64m  },
-  { X86::FpCHS32     , X86::FCHS     },
-  { X86::FpCHS64     , X86::FCHS     },
-  { X86::FpCMOVB32   , X86::FCMOVB   },
-  { X86::FpCMOVB64   , X86::FCMOVB  },
-  { X86::FpCMOVBE32  , X86::FCMOVBE  },
-  { X86::FpCMOVBE64  , X86::FCMOVBE  },
-  { X86::FpCMOVE32   , X86::FCMOVE  },
-  { X86::FpCMOVE64   , X86::FCMOVE   },
-  { X86::FpCMOVNB32  , X86::FCMOVNB  },
-  { X86::FpCMOVNB64  , X86::FCMOVNB  },
-  { X86::FpCMOVNBE32 , X86::FCMOVNBE },
-  { X86::FpCMOVNBE64 , X86::FCMOVNBE },
-  { X86::FpCMOVNE32  , X86::FCMOVNE  },
-  { X86::FpCMOVNE64  , X86::FCMOVNE  },
-  { X86::FpCMOVNP32  , X86::FCMOVNP  },
-  { X86::FpCMOVNP64  , X86::FCMOVNP  },
-  { X86::FpCMOVP32   , X86::FCMOVP   },
-  { X86::FpCMOVP64   , X86::FCMOVP   },
-  { X86::FpCOS32     , X86::FCOS     },
-  { X86::FpCOS64     , X86::FCOS     },
-  { X86::FpDIV32m    , X86::FDIV32m  },
-  { X86::FpDIV64m    , X86::FDIV64m  },
-  { X86::FpDIVR32m   , X86::FDIVR32m },
-  { X86::FpDIVR64m   , X86::FDIVR64m },
-  { X86::FpIADD16m32 , X86::FIADD16m },
-  { X86::FpIADD16m64 , X86::FIADD16m },
-  { X86::FpIADD32m32 , X86::FIADD32m },
-  { X86::FpIADD32m64 , X86::FIADD32m },
-  { X86::FpIDIV16m32 , X86::FIDIV16m },
-  { X86::FpIDIV16m64 , X86::FIDIV16m },
-  { X86::FpIDIV32m32 , X86::FIDIV32m },
-  { X86::FpIDIV32m64 , X86::FIDIV32m },
-  { X86::FpIDIVR16m32, X86::FIDIVR16m},
-  { X86::FpIDIVR16m64, X86::FIDIVR16m},
-  { X86::FpIDIVR32m32, X86::FIDIVR32m},
-  { X86::FpIDIVR32m64, X86::FIDIVR32m},
-  { X86::FpILD16m32  , X86::FILD16m  },
-  { X86::FpILD16m64  , X86::FILD16m  },
-  { X86::FpILD32m32  , X86::FILD32m  },
-  { X86::FpILD32m64  , X86::FILD32m  },
-  { X86::FpILD64m32  , X86::FILD64m  },
-  { X86::FpILD64m64  , X86::FILD64m  },
-  { X86::FpIMUL16m32 , X86::FIMUL16m },
-  { X86::FpIMUL16m64 , X86::FIMUL16m },
-  { X86::FpIMUL32m32 , X86::FIMUL32m },
-  { X86::FpIMUL32m64 , X86::FIMUL32m },
-  { X86::FpIST16m32  , X86::FIST16m  },
-  { X86::FpIST16m64  , X86::FIST16m  },
-  { X86::FpIST32m32  , X86::FIST32m  },
-  { X86::FpIST32m64  , X86::FIST32m  },
-  { X86::FpIST64m32  , X86::FISTP64m },
-  { X86::FpIST64m64  , X86::FISTP64m },
-  { X86::FpISTT16m32 , X86::FISTTP16m},
-  { X86::FpISTT16m64 , X86::FISTTP16m},
-  { X86::FpISTT32m32 , X86::FISTTP32m},
-  { X86::FpISTT32m64 , X86::FISTTP32m},
-  { X86::FpISTT64m32 , X86::FISTTP64m},
-  { X86::FpISTT64m64 , X86::FISTTP64m},
-  { X86::FpISUB16m32 , X86::FISUB16m },
-  { X86::FpISUB16m64 , X86::FISUB16m },
-  { X86::FpISUB32m32 , X86::FISUB32m },
-  { X86::FpISUB32m64 , X86::FISUB32m },
-  { X86::FpISUBR16m32, X86::FISUBR16m},
-  { X86::FpISUBR16m64, X86::FISUBR16m},
-  { X86::FpISUBR32m32, X86::FISUBR32m},
-  { X86::FpISUBR32m64, X86::FISUBR32m},
-  { X86::FpLD032     , X86::FLD0     },
-  { X86::FpLD064     , X86::FLD0     },
-  { X86::FpLD132     , X86::FLD1     },
-  { X86::FpLD164     , X86::FLD1     },
-  { X86::FpLD32m     , X86::FLD32m   },
-  { X86::FpLD64m     , X86::FLD64m   },
-  { X86::FpMUL32m    , X86::FMUL32m  },
-  { X86::FpMUL64m    , X86::FMUL64m  },
-  { X86::FpSIN32     , X86::FSIN     },
-  { X86::FpSIN64     , X86::FSIN     },
-  { X86::FpSQRT32    , X86::FSQRT    },
-  { X86::FpSQRT64    , X86::FSQRT    },
-  { X86::FpST32m     , X86::FST32m   },
-  { X86::FpST64m     , X86::FST64m   },
-  { X86::FpST64m32   , X86::FST32m   },
-  { X86::FpSUB32m    , X86::FSUB32m  },
-  { X86::FpSUB64m    , X86::FSUB64m  },
-  { X86::FpSUBR32m   , X86::FSUBR32m },
-  { X86::FpSUBR64m   , X86::FSUBR64m },
-  { X86::FpTST32     , X86::FTST     },
-  { X86::FpTST64     , X86::FTST     },
-  { X86::FpUCOMIr32  , X86::FUCOMIr  },
-  { X86::FpUCOMIr64  , X86::FUCOMIr  },
-  { X86::FpUCOMr32   , X86::FUCOMr   },
-  { X86::FpUCOMr64   , X86::FUCOMr   },
+  { X86::ABS_Fp32     , X86::ABS_F     },
+  { X86::ABS_Fp64     , X86::ABS_F     },
+  { X86::ADD_Fp32m   , X86::ADD_F32m  },
+  { X86::ADD_Fp64m   , X86::ADD_F64m  },
+  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
+  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
+  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
+  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
+  { X86::CHS_Fp32     , X86::CHS_F     },
+  { X86::CHS_Fp64     , X86::CHS_F     },
+  { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
+  { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
+  { X86::CMOVB_Fp32   , X86::CMOVB_F   },
+  { X86::CMOVB_Fp64   , X86::CMOVB_F  },
+  { X86::CMOVE_Fp32   , X86::CMOVE_F  },
+  { X86::CMOVE_Fp64   , X86::CMOVE_F   },
+  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
+  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
+  { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
+  { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
+  { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
+  { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
+  { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
+  { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
+  { X86::CMOVP_Fp32   , X86::CMOVP_F   },
+  { X86::CMOVP_Fp64   , X86::CMOVP_F   },
+  { X86::COS_Fp32     , X86::COS_F     },
+  { X86::COS_Fp64     , X86::COS_F     },
+  { X86::DIVR_Fp32m   , X86::DIVR_F32m },
+  { X86::DIVR_Fp64m   , X86::DIVR_F64m },
+  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
+  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
+  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
+  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
+  { X86::DIV_Fp32m    , X86::DIV_F32m  },
+  { X86::DIV_Fp64m    , X86::DIV_F64m  },
+  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
+  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
+  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
+  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
+  { X86::ILD_Fp16m32  , X86::ILD_F16m  },
+  { X86::ILD_Fp16m64  , X86::ILD_F16m  },
+  { X86::ILD_Fp32m32  , X86::ILD_F32m  },
+  { X86::ILD_Fp32m64  , X86::ILD_F32m  },
+  { X86::ILD_Fp64m32  , X86::ILD_F64m  },
+  { X86::ILD_Fp64m64  , X86::ILD_F64m  },
+  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
+  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
+  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
+  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
+  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
+  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
+  { X86::IST_Fp16m32  , X86::IST_F16m  },
+  { X86::IST_Fp16m64  , X86::IST_F16m  },
+  { X86::IST_Fp32m32  , X86::IST_F32m  },
+  { X86::IST_Fp32m64  , X86::IST_F32m  },
+  { X86::IST_Fp64m32  , X86::IST_FP64m },
+  { X86::IST_Fp64m64  , X86::IST_FP64m },
+  { X86::LD_Fp032     , X86::LD_F0     },
+  { X86::LD_Fp064     , X86::LD_F0     },
+  { X86::LD_Fp132     , X86::LD_F1     },
+  { X86::LD_Fp164     , X86::LD_F1     },
+  { X86::LD_Fp32m     , X86::LD_F32m   },
+  { X86::LD_Fp64m     , X86::LD_F64m   },
+  { X86::MUL_Fp32m    , X86::MUL_F32m  },
+  { X86::MUL_Fp64m    , X86::MUL_F64m  },
+  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
+  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
+  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
+  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
+  { X86::SIN_Fp32     , X86::SIN_F     },
+  { X86::SIN_Fp64     , X86::SIN_F     },
+  { X86::SQRT_Fp32    , X86::SQRT_F    },
+  { X86::SQRT_Fp64    , X86::SQRT_F    },
+  { X86::ST_Fp32m     , X86::ST_F32m   },
+  { X86::ST_Fp64m     , X86::ST_F64m   },
+  { X86::ST_Fp64m32   , X86::ST_F32m   },
+  { X86::SUBR_Fp32m   , X86::SUBR_F32m },
+  { X86::SUBR_Fp64m   , X86::SUBR_F64m },
+  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
+  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
+  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
+  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
+  { X86::SUB_Fp32m    , X86::SUB_F32m  },
+  { X86::SUB_Fp64m    , X86::SUB_F64m  },
+  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
+  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
+  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
+  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
+  { X86::TST_Fp32     , X86::TST_F     },
+  { X86::TST_Fp64     , X86::TST_F     },
+  { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
+  { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
+  { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
+  { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
 };
 
 static unsigned getConcreteOpcode(unsigned Opcode) {
@@ -436,27 +436,27 @@ static unsigned getConcreteOpcode(unsigned Opcode) {
 // element is an instruction, the second is the version which pops.
 //
 static const TableEntry PopTable[] = {
-  { X86::FADDrST0 , X86::FADDPrST0  },
+  { X86::ADD_FrST0 , X86::ADD_FPrST0  },
 
-  { X86::FDIVRrST0, X86::FDIVRPrST0 },
-  { X86::FDIVrST0 , X86::FDIVPrST0  },
+  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
+  { X86::DIV_FrST0 , X86::DIV_FPrST0  },
 
-  { X86::FIST16m  , X86::FISTP16m   },
-  { X86::FIST32m  , X86::FISTP32m   },
+  { X86::IST_F16m  , X86::IST_FP16m   },
+  { X86::IST_F32m  , X86::IST_FP32m   },
 
-  { X86::FMULrST0 , X86::FMULPrST0  },
+  { X86::MUL_FrST0 , X86::MUL_FPrST0  },
 
-  { X86::FST32m   , X86::FSTP32m    },
-  { X86::FST64m   , X86::FSTP64m    },
-  { X86::FSTrr    , X86::FSTPrr     },
+  { X86::ST_F32m   , X86::ST_FP32m    },
+  { X86::ST_F64m   , X86::ST_FP64m    },
+  { X86::ST_Frr    , X86::ST_FPrr     },
 
-  { X86::FSUBRrST0, X86::FSUBRPrST0 },
-  { X86::FSUBrST0 , X86::FSUBPrST0  },
+  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
+  { X86::SUB_FrST0 , X86::SUB_FPrST0  },
 
-  { X86::FUCOMIr  , X86::FUCOMIPr   },
+  { X86::UCOM_FIr  , X86::UCOM_FIPr   },
 
-  { X86::FUCOMPr  , X86::FUCOMPPr   },
-  { X86::FUCOMr   , X86::FUCOMPr    },
+  { X86::UCOM_FPr  , X86::UCOM_FPPr   },
+  { X86::UCOM_Fr   , X86::UCOM_FPr    },
 };
 
 /// popStackAfter - Pop the current value off of the top of the FP stack after
@@ -474,10 +474,10 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
   int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
   if (Opcode != -1) {
     I->setInstrDescriptor(TII->get(Opcode));
-    if (Opcode == X86::FUCOMPPr)
+    if (Opcode == X86::UCOM_FPPr)
       I->RemoveOperand(0);
   } else {    // Insert an explicit pop
-    I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0);
+    I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
   }
 }
 
@@ -501,7 +501,7 @@ void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
   RegMap[TopReg]    = OldSlot;
   RegMap[FPRegNo]   = ~0;
   Stack[--StackTop] = ~0;
-  I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg);
+  I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
 }
 
 
@@ -550,14 +550,14 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
   // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
   //
   if (!KillsSrc &&
-      (MI->getOpcode() == X86::FpIST64m32 ||
-       MI->getOpcode() == X86::FpISTT16m32 ||
-       MI->getOpcode() == X86::FpISTT32m32 ||
-       MI->getOpcode() == X86::FpISTT64m32 ||
-       MI->getOpcode() == X86::FpIST64m64 ||
-       MI->getOpcode() == X86::FpISTT16m64 ||
-       MI->getOpcode() == X86::FpISTT32m64 ||
-       MI->getOpcode() == X86::FpISTT64m64)) {
+      (MI->getOpcode() == X86::IST_Fp64m32 ||
+       MI->getOpcode() == X86::ISTT_Fp16m32 ||
+       MI->getOpcode() == X86::ISTT_Fp32m32 ||
+       MI->getOpcode() == X86::ISTT_Fp64m32 ||
+       MI->getOpcode() == X86::IST_Fp64m64 ||
+       MI->getOpcode() == X86::ISTT_Fp16m64 ||
+       MI->getOpcode() == X86::ISTT_Fp32m64 ||
+       MI->getOpcode() == X86::ISTT_Fp64m64)) {
     duplicateToTop(Reg, 7 /*temp register*/, I);
   } else {
     moveToTop(Reg, I);            // Move to the top of the stack...
@@ -567,10 +567,10 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
   MI->RemoveOperand(NumOps-1);    // Remove explicit ST(0) operand
   MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
 
-  if (MI->getOpcode() == X86::FISTP64m ||
-      MI->getOpcode() == X86::FISTTP16m ||
-      MI->getOpcode() == X86::FISTTP32m ||
-      MI->getOpcode() == X86::FISTTP64m) {
+  if (MI->getOpcode() == X86::IST_FP64m ||
+      MI->getOpcode() == X86::ISTT_FP16m ||
+      MI->getOpcode() == X86::ISTT_FP32m ||
+      MI->getOpcode() == X86::ISTT_FP64m) {
     assert(StackTop > 0 && "Stack empty??");
     --StackTop;
   } else if (KillsSrc) { // Last use of operand?
@@ -622,50 +622,50 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
 
 // ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
 static const TableEntry ForwardST0Table[] = {
-  { X86::FpADD32  , X86::FADDST0r },
-  { X86::FpADD64  , X86::FADDST0r },
-  { X86::FpDIV32  , X86::FDIVST0r },
-  { X86::FpDIV64  , X86::FDIVST0r },
-  { X86::FpMUL32  , X86::FMULST0r },
-  { X86::FpMUL64  , X86::FMULST0r },
-  { X86::FpSUB32  , X86::FSUBST0r },
-  { X86::FpSUB64  , X86::FSUBST0r },
+  { X86::ADD_Fp32  , X86::ADD_FST0r },
+  { X86::ADD_Fp64  , X86::ADD_FST0r },
+  { X86::DIV_Fp32  , X86::DIV_FST0r },
+  { X86::DIV_Fp64  , X86::DIV_FST0r },
+  { X86::MUL_Fp32  , X86::MUL_FST0r },
+  { X86::MUL_Fp64  , X86::MUL_FST0r },
+  { X86::SUB_Fp32  , X86::SUB_FST0r },
+  { X86::SUB_Fp64  , X86::SUB_FST0r },
 };
 
 // ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
 static const TableEntry ReverseST0Table[] = {
-  { X86::FpADD32  , X86::FADDST0r  },   // commutative
-  { X86::FpADD64  , X86::FADDST0r  },   // commutative
-  { X86::FpDIV32  , X86::FDIVRST0r },
-  { X86::FpDIV64  , X86::FDIVRST0r },
-  { X86::FpMUL32  , X86::FMULST0r  },   // commutative
-  { X86::FpMUL64  , X86::FMULST0r  },   // commutative
-  { X86::FpSUB32  , X86::FSUBRST0r },
-  { X86::FpSUB64  , X86::FSUBRST0r },
+  { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
+  { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
+  { X86::DIV_Fp32  , X86::DIVR_FST0r },
+  { X86::DIV_Fp64  , X86::DIVR_FST0r },
+  { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
+  { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
+  { X86::SUB_Fp32  , X86::SUBR_FST0r },
+  { X86::SUB_Fp64  , X86::SUBR_FST0r },
 };
 
 // ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
 static const TableEntry ForwardSTiTable[] = {
-  { X86::FpADD32  , X86::FADDrST0  },   // commutative
-  { X86::FpADD64  , X86::FADDrST0  },   // commutative
-  { X86::FpDIV32  , X86::FDIVRrST0 },
-  { X86::FpDIV64  , X86::FDIVRrST0 },
-  { X86::FpMUL32  , X86::FMULrST0  },   // commutative
-  { X86::FpMUL64  , X86::FMULrST0  },   // commutative
-  { X86::FpSUB32  , X86::FSUBRrST0 },
-  { X86::FpSUB64  , X86::FSUBRrST0 },
+  { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
+  { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
+  { X86::DIV_Fp32  , X86::DIVR_FrST0 },
+  { X86::DIV_Fp64  , X86::DIVR_FrST0 },
+  { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
+  { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
+  { X86::SUB_Fp32  , X86::SUBR_FrST0 },
+  { X86::SUB_Fp64  , X86::SUBR_FrST0 },
 };
 
 // ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
 static const TableEntry ReverseSTiTable[] = {
-  { X86::FpADD32  , X86::FADDrST0 },
-  { X86::FpADD64  , X86::FADDrST0 },
-  { X86::FpDIV32  , X86::FDIVrST0 },
-  { X86::FpDIV64  , X86::FDIVrST0 },
-  { X86::FpMUL32  , X86::FMULrST0 },
-  { X86::FpMUL64  , X86::FMULrST0 },
-  { X86::FpSUB32  , X86::FSUBrST0 },
-  { X86::FpSUB64  , X86::FSUBrST0 },
+  { X86::ADD_Fp32  , X86::ADD_FrST0 },
+  { X86::ADD_Fp64  , X86::ADD_FrST0 },
+  { X86::DIV_Fp32  , X86::DIV_FrST0 },
+  { X86::DIV_Fp64  , X86::DIV_FrST0 },
+  { X86::MUL_Fp32  , X86::MUL_FrST0 },
+  { X86::MUL_Fp64  , X86::MUL_FrST0 },
+  { X86::SUB_Fp32  , X86::SUB_FrST0 },
+  { X86::SUB_Fp64  , X86::SUB_FrST0 },
 };
 
 
@@ -847,10 +847,10 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
     assert(StackTop == 1 && "Stack should have one element on it to return!");
     --StackTop;   // "Forget" we have something on the top of stack!
     break;
-  case X86::FpMOV3232:
-  case X86::FpMOV3264:
-  case X86::FpMOV6432:
-  case X86::FpMOV6464: {
+  case X86::MOV_Fp3232:
+  case X86::MOV_Fp3264:
+  case X86::MOV_Fp6432:
+  case X86::MOV_Fp6464: {
     unsigned SrcReg = getFPReg(MI->getOperand(1));
     unsigned DestReg = getFPReg(MI->getOperand(0));
 
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 641ccb03de..939cfd556a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4468,12 +4468,12 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
     unsigned Opc;
     switch (MI->getOpcode()) {
     default: assert(0 && "illegal opcode!");
-    case X86::FP32_TO_INT16_IN_MEM: Opc = X86::FpIST16m32; break;
-    case X86::FP32_TO_INT32_IN_MEM: Opc = X86::FpIST32m32; break;
-    case X86::FP32_TO_INT64_IN_MEM: Opc = X86::FpIST64m32; break;
-    case X86::FP64_TO_INT16_IN_MEM: Opc = X86::FpIST16m64; break;
-    case X86::FP64_TO_INT32_IN_MEM: Opc = X86::FpIST32m64; break;
-    case X86::FP64_TO_INT64_IN_MEM: Opc = X86::FpIST64m64; break;
+    case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
+    case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
+    case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
+    case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
+    case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
+    case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
     }
 
     X86AddressMode AM;
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index 668fe96e11..6c1f42ca8f 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -66,8 +66,6 @@ def fpimmneg1 : PatLeaf<(fpimm), [{
   return N->isExactlyValue(-1.0);
 }]>;
 
-def extloadf64f32  : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>;
-
 // Some 'special' instructions
 let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
   def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
@@ -100,13 +98,20 @@ let isTerminator = 1 in
   let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
     def FP_REG_KILL  : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
 
-// All FP Stack operations are represented with two instructions here.  The
-// first instruction, generated by the instruction selector, uses "RFP"
-// registers: a traditional register file to reference floating point values.
-// These instructions are all psuedo instructions and use the "Fp" prefix.
+// All FP Stack operations are represented with three instructions here.  The
+// first two instructions, generated by the instruction selector, uses "RFP32"
+// or "RFP64" registers: traditional register files to reference 32-bit or
+// 64-bit floating point values.  These sizes apply to the values, not the
+// registers, which are always 64 bits; RFP32 and RFP64 can be copied to
+// each other without losing information.  These instructions are all psuedo
+// instructions and use the "_Fp" suffix.
+// In some cases there are additional variants with a mixture of 32-bit and
+// 64-bit registers.
 // The second instruction is defined with FPI, which is the actual instruction
-// emitted by the assembler.  The FP stackifier pass converts one to the other
-// after register allocation occurs.
+// emitted by the assembler.  These use "RST" registers, although frequently
+// the actual register(s) used are implicit.  These are always 64-bits.
+// The FP stackifier pass converts one to the other after register allocation 
+// occurs.
 //
 // Note that the FpI instruction should have instruction selection info (e.g.
 // a pattern) and the FPI instruction should have emission info (e.g. opcode
@@ -141,29 +146,57 @@ class FpI<dag ops, FPFormat fp, list<dag> pattern> :
   FpI_<ops, fp, pattern>, Requires<[FPStack]>;
 
 // Register copies.  Just copies, the 64->32 version does not truncate.
-def FpMOV3232       : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2
-def FpMOV3264       : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2
-def FpMOV6432       : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2
-def FpMOV6464       : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2
-
-// Arithmetic
-// Add, Sub, Mul, Div.
-def FpADD32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
-                [(set RFP32:$dst, (fadd RFP32:$src1, RFP32:$src2))]>;
-def FpSUB32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
-                [(set RFP32:$dst, (fsub RFP32:$src1, RFP32:$src2))]>;
-def FpMUL32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
-                [(set RFP32:$dst, (fmul RFP32:$src1, RFP32:$src2))]>;
-def FpDIV32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
-                [(set RFP32:$dst, (fdiv RFP32:$src1, RFP32:$src2))]>;
-def FpADD64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
-                [(set RFP64:$dst, (fadd RFP64:$src1, RFP64:$src2))]>;
-def FpSUB64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
-                [(set RFP64:$dst, (fsub RFP64:$src1, RFP64:$src2))]>;
-def FpMUL64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
-                [(set RFP64:$dst, (fmul RFP64:$src1, RFP64:$src2))]>;
-def FpDIV64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
-                [(set RFP64:$dst, (fdiv RFP64:$src1, RFP64:$src2))]>;
+def MOV_Fp3232       : FpI<(ops RFP32:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2
+def MOV_Fp3264       : FpI<(ops RFP64:$dst, RFP32:$src), SpecialFP, []>; // f1 = fmov f2
+def MOV_Fp6432       : FpI<(ops RFP32:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2
+def MOV_Fp6464       : FpI<(ops RFP64:$dst, RFP64:$src), SpecialFP, []>; // f1 = fmov f2
+
+// Factoring for arithmetic.
+multiclass FPBinary_rr<SDNode OpNode> {
+// Register op register -> register
+// These are separated out because they have no reversed form.
+def _Fp32 : FpI<(ops RFP32:$dst, RFP32:$src1, RFP32:$src2), TwoArgFP,
+                [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
+def _Fp64 : FpI<(ops RFP64:$dst, RFP64:$src1, RFP64:$src2), TwoArgFP,
+                [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
+}
+// The FopST0 series are not included here because of the irregularities
+// in where the 'r' goes in assembly output.
+multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
+// ST(0) = ST(0) + [mem]
+def _Fp32m  : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
+                  [(set RFP32:$dst, (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
+def _Fp64m  : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
+                  [(set RFP64:$dst, (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
+def _F32m  : FPI<0xD8, fp, (ops f32mem:$src), !strconcat("f", !strconcat(asmstring, "{s} $src"))>;
+def _F64m  : FPI<0xDC, fp, (ops f64mem:$src), !strconcat("f", !strconcat(asmstring, "{l} $src"))>;
+// ST(0) = ST(0) + [memint]
+def _FpI16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP32:$dst, (OpNode RFP32:$src1,
+                                       (X86fild addr:$src2, i16)))]>;
+def _FpI32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
+                    [(set RFP32:$dst, (OpNode RFP32:$src1,
+                                       (X86fild addr:$src2, i32)))]>;
+def _FpI16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP64:$dst, (OpNode RFP64:$src1,
+                                       (X86fild addr:$src2, i16)))]>;
+def _FpI32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
+                    [(set RFP64:$dst, (OpNode RFP64:$src1,
+                                       (X86fild addr:$src2, i32)))]>;
+def _FI16m  : FPI<0xDE, fp, (ops i16mem:$src), !strconcat("fi", !strconcat(asmstring, "{s} $src"))>;
+def _FI32m  : FPI<0xDA, fp, (ops i32mem:$src), !strconcat("fi", !strconcat(asmstring, "{l} $src"))>;
+}
+
+defm ADD : FPBinary_rr<fadd>;
+defm SUB : FPBinary_rr<fsub>;
+defm MUL : FPBinary_rr<fmul>;
+defm DIV : FPBinary_rr<fdiv>;
+defm ADD : FPBinary<fadd, MRM0m, "add">;
+defm SUB : FPBinary<fsub, MRM4m, "sub">;
+defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
+defm MUL : FPBinary<fmul, MRM1m, "mul">;
+defm DIV : FPBinary<fdiv, MRM6m, "div">;
+defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
 
 class FPST0rInst<bits<8> o, string asm>
   : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
@@ -172,416 +205,207 @@ class FPrST0Inst<bits<8> o, string asm>
 class FPrST0PInst<bits<8> o, string asm>
   : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
 
-// Binary Ops with a memory source.
-def FpADD32m  : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
-                  [(set RFP32:$dst, (fadd RFP32:$src1, (loadf32 addr:$src2)))]>;
-                // ST(0) = ST(0) + [mem32]
-def FpADD64m  : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
-                  [(set RFP64:$dst, (fadd RFP64:$src1, (loadf64 addr:$src2)))]>;
-                // ST(0) = ST(0) + [mem64]
-def FpMUL32m  : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
-                  [(set RFP32:$dst, (fmul RFP32:$src1, (loadf32 addr:$src2)))]>;
-                // ST(0) = ST(0) * [mem32]
-def FpMUL64m  : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
-                  [(set RFP64:$dst, (fmul RFP64:$src1, (loadf64 addr:$src2)))]>;
-                // ST(0) = ST(0) * [mem64]
-def FpSUB32m  : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
-                  [(set RFP32:$dst, (fsub RFP32:$src1, (loadf32 addr:$src2)))]>;
-                // ST(0) = ST(0) - [mem32]
-def FpSUB64m  : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
-                  [(set RFP64:$dst, (fsub RFP64:$src1, (loadf64 addr:$src2)))]>;
-                // ST(0) = ST(0) - [mem64]
-def FpSUBR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
-                  [(set RFP32:$dst, (fsub (loadf32 addr:$src2), RFP32:$src1))]>;
-                // ST(0) = [mem32] - ST(0)
-def FpSUBR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
-                  [(set RFP64:$dst, (fsub (loadf64 addr:$src2), RFP64:$src1))]>;
-                // ST(0) = [mem64] - ST(0)
-def FpDIV32m  : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
-                  [(set RFP32:$dst, (fdiv RFP32:$src1, (loadf32 addr:$src2)))]>;
-                // ST(0) = ST(0) / [mem32]
-def FpDIV64m  : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
-                  [(set RFP64:$dst, (fdiv RFP64:$src1, (loadf64 addr:$src2)))]>;
-                // ST(0) = ST(0) / [mem64]
-def FpDIVR32m : FpI<(ops RFP32:$dst, RFP32:$src1, f32mem:$src2), OneArgFPRW,
-                  [(set RFP32:$dst, (fdiv (loadf32 addr:$src2), RFP32:$src1))]>;
-                // ST(0) = [mem32] / ST(0)
-def FpDIVR64m : FpI<(ops RFP64:$dst, RFP64:$src1, f64mem:$src2), OneArgFPRW,
-                  [(set RFP64:$dst, (fdiv (loadf64 addr:$src2), RFP64:$src1))]>;
-                // ST(0) = [mem64] / ST(0)
-
-
-def FADD32m  : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">;
-def FADD64m  : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">;
-def FMUL32m  : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">;
-def FMUL64m  : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">;
-def FSUB32m  : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">;
-def FSUB64m  : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">;
-def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">;
-def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">;
-def FDIV32m  : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">;
-def FDIV64m  : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">;
-def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">;
-def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
-
-def FpIADD16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fadd RFP32:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) + [mem16int]
-def FpIADD32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fadd RFP32:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) + [mem32int]
-def FpIMUL16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fmul RFP32:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) * [mem16int]
-def FpIMUL32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fmul RFP32:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) * [mem32int]
-def FpISUB16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fsub RFP32:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) - [mem16int]
-def FpISUB32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fsub RFP32:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) - [mem32int]
-def FpISUBR16m32: FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fsub (X86fild addr:$src2, i16),
-                                       RFP32:$src1))]>;
-                  // ST(0) = [mem16int] - ST(0)
-def FpISUBR32m32: FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fsub (X86fild addr:$src2, i32),
-                                       RFP32:$src1))]>;
-                  // ST(0) = [mem32int] - ST(0)
-def FpIDIV16m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fdiv RFP32:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) / [mem16int]
-def FpIDIV32m32 : FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fdiv RFP32:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) / [mem32int]
-def FpIDIVR16m32: FpI<(ops RFP32:$dst, RFP32:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i16),
-                                       RFP32:$src1))]>;
-                  // ST(0) = [mem16int] / ST(0)
-def FpIDIVR32m32: FpI<(ops RFP32:$dst, RFP32:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP32:$dst, (fdiv (X86fild addr:$src2, i32),
-                                       RFP32:$src1))]>;
-                  // ST(0) = [mem32int] / ST(0)
-
-def FpIADD16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fadd RFP64:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) + [mem16int]
-def FpIADD32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fadd RFP64:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) + [mem32int]
-def FpIMUL16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fmul RFP64:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) * [mem16int]
-def FpIMUL32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fmul RFP64:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) * [mem32int]
-def FpISUB16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fsub RFP64:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) - [mem16int]
-def FpISUB32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fsub RFP64:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) - [mem32int]
-def FpISUBR16m64: FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
-                     [(set RFP64:$dst, (fsub (X86fild addr:$src2, i16),
-                                        RFP64:$src1))]>;
-                  // ST(0) = [mem16int] - ST(0)
-def FpISUBR32m64: FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fsub (X86fild addr:$src2, i32),
-                                       RFP64:$src1))]>;
-                  // ST(0) = [mem32int] - ST(0)
-def FpIDIV16m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fdiv RFP64:$src1,
-                                       (X86fild addr:$src2, i16)))]>;
-                  // ST(0) = ST(0) / [mem16int]
-def FpIDIV32m64 : FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fdiv RFP64:$src1,
-                                       (X86fild addr:$src2, i32)))]>;
-                  // ST(0) = ST(0) / [mem32int]
-def FpIDIVR16m64: FpI<(ops RFP64:$dst, RFP64:$src1, i16mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i16),
-                                       RFP64:$src1))]>;
-                  // ST(0) = [mem16int] / ST(0)
-def FpIDIVR32m64: FpI<(ops RFP64:$dst, RFP64:$src1, i32mem:$src2), OneArgFPRW,
-                    [(set RFP64:$dst, (fdiv (X86fild addr:$src2, i32),
-                                       RFP64:$src1))]>;
-                  // ST(0) = [mem32int] / ST(0)
-
-def FIADD16m  : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
-def FIADD32m  : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
-def FIMUL16m  : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
-def FIMUL32m  : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
-def FISUB16m  : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
-def FISUB32m  : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
-def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
-def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
-def FIDIV16m  : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
-def FIDIV32m  : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{l} $src">;
-def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
-def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{l} $src">;
-
 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
 // of some of the 'reverse' forms of the fsub and fdiv instructions.  As such,
 // we have to put some 'r's in and take them out of weird places.
-def FADDST0r   : FPST0rInst <0xC0, "fadd $op">;
-def FADDrST0   : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
-def FADDPrST0  : FPrST0PInst<0xC0, "faddp $op">;
-def FSUBRST0r  : FPST0rInst <0xE8, "fsubr $op">;
-def FSUBrST0   : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
-def FSUBPrST0  : FPrST0PInst<0xE8, "fsub{r}p $op">;
-def FSUBST0r   : FPST0rInst <0xE0, "fsub $op">;
-def FSUBRrST0  : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
-def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
-def FMULST0r   : FPST0rInst <0xC8, "fmul $op">;
-def FMULrST0   : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
-def FMULPrST0  : FPrST0PInst<0xC8, "fmulp $op">;
-def FDIVRST0r  : FPST0rInst <0xF8, "fdivr $op">;
-def FDIVrST0   : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
-def FDIVPrST0  : FPrST0PInst<0xF8, "fdiv{r}p $op">;
-def FDIVST0r   : FPST0rInst <0xF0, "fdiv $op">;
-def FDIVRrST0  : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
-def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
+def ADD_FST0r   : FPST0rInst <0xC0, "fadd $op">;
+def ADD_FrST0   : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
+def ADD_FPrST0  : FPrST0PInst<0xC0, "faddp $op">;
+def SUBR_FST0r  : FPST0rInst <0xE8, "fsubr $op">;
+def SUB_FrST0   : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
+def SUB_FPrST0  : FPrST0PInst<0xE8, "fsub{r}p $op">;
+def SUB_FST0r   : FPST0rInst <0xE0, "fsub $op">;
+def SUBR_FrST0  : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
+def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
+def MUL_FST0r   : FPST0rInst <0xC8, "fmul $op">;
+def MUL_FrST0   : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
+def MUL_FPrST0  : FPrST0PInst<0xC8, "fmulp $op">;
+def DIVR_FST0r  : FPST0rInst <0xF8, "fdivr $op">;
+def DIV_FrST0   : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
+def DIV_FPrST0  : FPrST0PInst<0xF8, "fdiv{r}p $op">;
+def DIV_FST0r   : FPST0rInst <0xF0, "fdiv $op">;
+def DIVR_FrST0  : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;