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| author | Jim Grosbach <grosbach@apple.com> | 2010-09-07 21:30:25 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-07 21:30:25 +0000 |
| commit | e2f70d1724a8336f5dd455fea7ec3d71592a2fa7 (patch) | |
| tree | da7d3f8c47b4eaa9e51a91dfc28933ff86ca1f40 | |
| parent | 7f6d62aaf9d0d9d84ec9301770221a5d40b0f4f8 (diff) | |
grammar tweak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113289 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index a13ff12327..da2efb8566 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -535,7 +535,7 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, // Load / store multiple Instructions. // -// These requires base address to be written back or one of the loaded regs. +// These require base address to be written back or one of the loaded regs. let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { def tLDM : T1I<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), |