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| author | Evan Cheng <evan.cheng@apple.com> | 2006-04-11 18:04:57 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-04-11 18:04:57 +0000 |
| commit | df3c33c57e16eb32c88bd1160fd9b6369ab23832 (patch) | |
| tree | de5cde00cde2fdd3f7fbd0ef2be789ceedf76cad | |
| parent | 135c6a9d838dfd85835eb7756cba81f7dc297db4 (diff) | |
gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support
later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27591 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/IntrinsicsX86.td | 3 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 12 |
2 files changed, 4 insertions, 11 deletions
diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index 8bb0d95a4c..48f79d25a2 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -139,9 +139,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". // Cacheability support ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". - def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">, - Intrinsic<[llvm_void_ty, llvm_ptr_ty, - llvm_int_ty], [IntrWriteMem]>; def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">, Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_v4f32_ty], [IntrWriteMem]>; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 9bb1f743c1..10f4d56276 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1517,17 +1517,13 @@ def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask), // Prefetching loads def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), - "prefetcht0 $src", - [(int_x86_sse_prefetch addr:$src, 1)]>; + "prefetcht0 $src", []>; def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), - "prefetcht1 $src", - [(int_x86_sse_prefetch addr:$src, 2)]>; + "prefetcht1 $src", []>; def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), - "prefetcht2 $src", - [(int_x86_sse_prefetch addr:$src, 3)]>; + "prefetcht2 $src", []>; def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), - "prefetchtnta $src", - [(int_x86_sse_prefetch addr:$src, 0)]>; + "prefetchtnta $src", []>; // Non-temporal stores def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src), |