Fix a thinko. If the operand is promoted, pass the promoted value into

the new zero extend, not the original operand.  This fixes cast bool -> long
on ppc.

Add an unrelated fixme


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21196 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 5 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 256aa2513e..1fcaa723e2 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1937,7 +1937,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
 
     // The low part is just a zero extension of the input (which degenerates to
     // a copy).
-    Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, LegalizeOp(Node->getOperand(0)));
+    Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
     
     // The high part is just a zero.
     Hi = DAG.getConstant(0, NVT);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 74e807ca82..f33ecd7223 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -767,6 +767,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
       if (N2C->isAllOnesValue())
 	return N1;                // X and -1 -> X
 
+      // FIXME: Should add a corresponding version of this for
+      // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
+      // we don't have yet.
+
       // and (zero_extend_inreg x:16:32), 1 -> and x, 1
       if (N1.getOpcode() == ISD::ZERO_EXTEND_INREG ||
           N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {