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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-23 02:04:38 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-23 02:04:38 +0000 |
| commit | dd9dd6f857604abdeb5213648ffe50c10ccc59b9 (patch) | |
| tree | 290b88ccbf16b8aa21c70b4a9d9db15a313b44de | |
| parent | 7871687604944d68455a777c3047ff2a6ca5985f (diff) | |
Latency between CPSR def and branch is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 0b5b2437ab..8399cd5ff4 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1892,7 +1892,13 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, if (!ItinData || ItinData->isEmpty()) return DefTID.mayLoad() ? 3 : 1; + const TargetInstrDesc &UseTID = UseMI->getDesc(); + const MachineOperand &DefMO = DefMI->getOperand(DefIdx); + if (DefMO.getReg() == ARM::CPSR && UseTID.isBranch()) + // CPSR set and branch can be paired in the same cycle. + return 0; + unsigned DefAlign = DefMI->hasOneMemOperand() ? (*DefMI->memoperands_begin())->getAlignment() : 0; unsigned UseAlign = UseMI->hasOneMemOperand() |