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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:47 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:47 +0000 |
| commit | dc0bab70cfc0fe2f80e0b4c310581f4cfa57bfe4 (patch) | |
| tree | 5135030bf1ca7519c24c7d8eb9c9138221a5604c | |
| parent | 0a3e2b591c0f5ae5d31aeb2eb794b3c5c38ffa98 (diff) | |
Fix itins for VPAL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV7.td | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMScheduleV7.td b/lib/Target/ARM/ARMScheduleV7.td index d313754afb..03b0ce891f 100644 --- a/lib/Target/ARM/ARMScheduleV7.td +++ b/lib/Target/ARM/ARMScheduleV7.td @@ -516,11 +516,11 @@ def CortexA8Itineraries : ProcessorItineraries<[ // // Double-register Integer Pair Add Long InstrItinData<IIC_VPALiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>, + InstrStage<1, [FU_NPipe]>], [6, 3, 1]>, // // Quad-register Integer Pair Add Long InstrItinData<IIC_VPALiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>, + InstrStage<2, [FU_NPipe]>], [7, 3, 1]>, // // Double-register Absolute Difference and Accumulate InstrItinData<IIC_VABAD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, @@ -923,7 +923,21 @@ def CortexA9Itineraries : ProcessorItineraries<[ // Extra 3 latency cycle since wbck is 6 cycles InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]> + InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>, + // + // Double-register Integer Pair Add Long + InstrItinData<IIC_VPALiD, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<1, [FU_NPipe]>], [6, 3, 1]>, + // + // Quad-register Integer Pair Add Long + InstrItinData<IIC_VPALiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>, + // Extra 3 latency cycle since wbck is 6 cycles + InstrStage2<7, [FU_DRegsVFP], 0, Reserved>, + InstrStage<1, [FU_Pipe0, FU_Pipe1]>, + InstrStage<2, [FU_NPipe]>], [6, 3, 1]> ]>; |