diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-10-23 06:05:49 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-10-23 06:05:49 +0000 |
| commit | da8d96d1a1769d0614c46d9880ac3c21cbc8e74c (patch) | |
| tree | 9d4309fc6fb9c43889c290fa99f29424fe346990 | |
| parent | 15f74b3f4f371d5ef556644a7a2d61a0993a8053 (diff) | |
Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17182 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index fe518af246..8d539b859a 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -324,10 +324,13 @@ def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B), // XFX-Form instructions. Instructions that deal with SPRs // -def MFCTR : XFXForm_1_ext<31, 339, 9, 0, 0, (ops GPRC:$rT), "mfctr $rT">; -def MFLR : XFXForm_1_ext<31, 339, 8, 0, 0, (ops GPRC:$rT), "mflr $rT">; -def MTCTR : XFXForm_7_ext<31, 467, 9, 0, 0, (ops GPRC:$rS), "mtctr $rS">; -def MTLR : XFXForm_7_ext<31, 467, 8, 0, 0, (ops GPRC:$rS), "mtlr $rS">; +// Note that although LR should be listed as `8' and CTR as `9' in the SPR +// field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9 +// which means the SPR value needs to be multiplied by a factor of 32. +def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">; +def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">; +def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">; +def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">; // XS-Form instructions. Just 'sradi' |