diff options
| author | Duncan Sands <baldrick@free.fr> | 2008-07-01 08:00:49 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2008-07-01 08:00:49 +0000 |
| commit | d9ad8abc8e9759fe9fb38d0397f1ab7a04be9fd1 (patch) | |
| tree | b92eac295459eb89abbaedb50e4dc879209ab134 | |
| parent | 57ce0319b7eb4418aac910d9a094e57d983a64d2 (diff) | |
Highlight that getMergeValues optimization is
being suppressed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52952 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6923e84b97..2fbc25c96d 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4517,7 +4517,8 @@ SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { SDOperand Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0); // Use a MERGE_VALUES node to drop the chain result value. - return DAG.getMergeValues(DAG.getVTList(VT), &Res, 1, false).Val; + return DAG.getMergeValues(DAG.getVTList(VT), &Res, 1, + false /* Require a node with one-result */).Val; } SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { |