diff options
| author | Chris Lattner <sabre@nondot.org> | 2007-12-16 20:12:41 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-12-16 20:12:41 +0000 |
| commit | d7610e16fc1490f2a3a16a68f5059fd34196fbc9 (patch) | |
| tree | e982e601e51f5bccd5f0e577bfbac003ed39e53c | |
| parent | ece2c04d532d46405c085769d03173b392813eb3 (diff) | |
Fix the JIT encoding of cmp*ss, which aborts with this assertion currently:
X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'
I *think* this is right, but Evan, please verify. It also looks like
CMPSDrr and maybe others are missing this info. Evan, plz investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45074 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrFormats.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index 912376d196..1eda93b0e9 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -145,6 +145,8 @@ class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern> class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; +class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>; class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 65c7906c13..a4e76b3ce1 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -385,10 +385,10 @@ let isTwoAddress = 1 in { // Comparison instructions let isTwoAddress = 1 in { - def CMPSSrr : SSI<0xC2, MRMSrcReg, + def CMPSSrr : SSIi8<0xC2, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc), "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>; - def CMPSSrm : SSI<0xC2, MRMSrcMem, + def CMPSSrm : SSIi8<0xC2, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc), "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>; } @@ -405,12 +405,12 @@ def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2), // Aliases to match intrinsics which expect XMM operand(s). let isTwoAddress = 1 in { - def Int_CMPSSrr : SSI<0xC2, MRMSrcReg, + def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc), "cmp${cc}ss\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, VR128:$src, imm:$cc))]>; - def Int_CMPSSrm : SSI<0xC2, MRMSrcMem, + def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc), "cmp${cc}ss\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1, |