diff options
| author | Owen Anderson <resistor@mac.com> | 2011-05-05 17:59:04 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-05-05 17:59:04 +0000 |
| commit | d71867a8f4b1ab6ab8cc8f5b1a732184ec5bad1b (patch) | |
| tree | b604d54ec03aa8416f7927d55133eff283b40a24 | |
| parent | d96efb83c11454f511f6b16bbf1fb07d8a14ef66 (diff) | |
Allow FastISel of three-register-operand instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130934 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/CodeGen/FastISel.h | 9 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 24 |
2 files changed, 33 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index 10c4c33dde..dba4b6d4c0 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -241,6 +241,15 @@ protected: unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill); + /// FastEmitInst_rrr - Emit a MachineInstr with three register operands + /// and a result register in the given register class. + /// + unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, + const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + unsigned Op2, bool Op2IsKill); + /// FastEmitInst_ri - Emit a MachineInstr with a register operand, /// an immediate, and a result register in the given register class. /// diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 3af948288d..621e8efd40 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1097,6 +1097,30 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, return ResultReg; } +unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, + const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + unsigned Op2, bool Op2IsKill) { + unsigned ResultReg = createResultReg(RC); + const TargetInstrDesc &II = TII.get(MachineInstOpcode); + + if (II.getNumDefs() >= 1) + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) + .addReg(Op0, Op0IsKill * RegState::Kill) + .addReg(Op1, Op1IsKill * RegState::Kill) + .addReg(Op2, Op2IsKill * RegState::Kill); + else { + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) + .addReg(Op0, Op0IsKill * RegState::Kill) + .addReg(Op1, Op1IsKill * RegState::Kill) + .addReg(Op2, Op2IsKill * RegState::Kill); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), + ResultReg).addReg(II.ImplicitDefs[0]); + } + return ResultReg; +} + unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, |