diff options
| author | Eric Christopher <echristo@apple.com> | 2011-07-01 00:30:46 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2011-07-01 00:30:46 +0000 |
| commit | d5dc9eca2beece0faa85e7cbf17182fe7fcd0b36 (patch) | |
| tree | 04c8869b13a6ac816cdd353017ce17645919a260 | |
| parent | e1bff38386b0af24b5564c3d20888c7bbb045099 (diff) | |
Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/ARM/inlineasm3.ll | 20 |
2 files changed, 25 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 1141f42f14..4a78ad4bf2 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -7484,6 +7484,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const { case 'w': return C_RegisterClass; case 'h': return C_RegisterClass; case 'x': return C_RegisterClass; + case 't': return C_RegisterClass; } } else if (Constraint.size() == 2) { switch (Constraint[0]) { @@ -7563,6 +7564,10 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, if (VT.getSizeInBits() == 128) return RCPair(0U, ARM::QPR_8RegisterClass); break; + case 't': + if (VT == MVT::f32) + return RCPair(0U, ARM::SPRRegisterClass); + break; } } if (StringRef("{cc}").equals_lower(Constraint)) diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index f09deb39f8..00257e1cdb 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -68,3 +68,23 @@ entry: %0 = tail call float asm "flds s15, $0", "=x"() nounwind ret float %0 } + +; Radar 9307836 & 9119939 + +define double @t7(double %y) nounwind ssp { +entry: +; CHECK: t7 +; CHECK: flds s15, d0 + %0 = tail call double asm "flds s15, $0", "=x"() nounwind + ret double %0 +} + +; Radar 9307836 & 9119939 + +define float @t8(float %y) nounwind ssp { +entry: +; CHECK: t8 +; CHECK: flds s15, s0 + %0 = tail call float asm "flds s15, $0", "=t"() nounwind + ret float %0 +} |