diff options
| author | Andrew Trick <atrick@apple.com> | 2011-04-29 14:18:15 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-04-29 14:18:15 +0000 |
| commit | d49ffe8284457953db68db063b527ee9c346b67a (patch) | |
| tree | 917702f45d3857a6665e9c282bf5ac8f06e3cb80 | |
| parent | a432997745f668e85e45826106430f69238b1d1e (diff) | |
Teach Thumb2 isel to fold and->rotr ==> ROR.
Generalization of Nate Begeman's patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 9 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/thumb2-ror.ll | 6 |
2 files changed, 13 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 165ae7e20a..5cfb7cd3ec 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -84,6 +84,11 @@ def imm0_255_not : PatLeaf<(i32 imm), [{ return (uint32_t)(~N->getZExtValue()) < 255; }], imm_comp_XFORM>; +def lo5AllOne : PatLeaf<(i32 imm), [{ + // Returns true if all low 5-bits are 1. + return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; +}]>; + // Define Thumb2 specific addressing modes. // t2addrmode_imm12 := reg + imm12 @@ -2023,6 +2028,10 @@ defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; +// (rotr x, (and y, 0x...1f)) ==> (ROR x, y) +def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), + (t2RORrr rGPR:$lhs, rGPR:$rhs)>; + let Uses = [CPSR] in { def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, "rrx", "\t$Rd, $Rm", diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll index c44fdb3ad5..590c333b3d 100644 --- a/test/CodeGen/Thumb2/thumb2-ror.ll +++ b/test/CodeGen/Thumb2/thumb2-ror.ll @@ -11,11 +11,13 @@ define i32 @f1(i32 %a) { } ; CHECK: f2: +; CHECK-NOT: and ; CHECK: ror define i32 @f2(i32 %v, i32 %nbits) { entry: - %shr = lshr i32 %v, %nbits - %sub = sub i32 32, %nbits + %and = and i32 %nbits, 31 + %shr = lshr i32 %v, %and + %sub = sub i32 32, %and %shl = shl i32 %v, %sub %or = or i32 %shl, %shr ret i32 %or |