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| author | Kevin Enderby <enderby@apple.com> | 2011-02-28 18:46:31 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2011-02-28 18:46:31 +0000 |
| commit | d436d5b1c993c78b6c267b5fc1056d593f07921f (patch) | |
| tree | 9099ce71b0aafe1fcf145601786919ee1a8d8148 | |
| parent | c24ab5c654debe47d5693e287d4dc2e151c0ba0e (diff) | |
Fix the arm's disassembler for blx that was building an MCInst without the
needed two predicate operands before the imm operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 14 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-tests.txt | 3 |
2 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 23372e0224..074561c02d 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1719,6 +1719,17 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode, return true; } + // Some instructions have predicate operands first before the immediate. + if(Opcode == ARM::tBLXi_r9 || Opcode == ARM::tBLr9) { + // Handling the two predicate operands before the imm operand. + if (B->DoPredicateOperands(MI, Opcode, insn, NumOps)) + NumOpsAdded += 2; + else { + DEBUG(errs() << "Expected predicate operands not found.\n"); + return false; + } + } + // Add the imm operand. int Offset = 0; @@ -1745,7 +1756,8 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode, // to compensate. MI.addOperand(MCOperand::CreateImm(Offset + 4)); - NumOpsAdded = 1; + // This is an increment as some predicate operands may have been added first. + NumOpsAdded += 1; return true; } diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 6dab1237a1..36f74381a5 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -118,3 +118,6 @@ # CHECK: msr cpsr_fc, r0 0x80 0xf3 0x00 0x89 + +# CHECK: blx #0 +0xff 0xf7 0xfe 0xef |