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| author | Kevin Enderby <enderby@apple.com> | 2011-03-02 23:08:33 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2011-03-02 23:08:33 +0000 |
| commit | d39647d9130a52beb80bdc9116cb0f3a8affe12f (patch) | |
| tree | 348f4afa0c55d366a147a406877386b2ac8653ce | |
| parent | 4670353a21fbc6e8159a129cda965f256e73a451 (diff) | |
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
Patch by Ted Kremenek!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 13 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 3 |
2 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 6e3fe2e039..173275b084 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2203,6 +2203,19 @@ def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, let Inst{19-16} = Rn; let Inst{11-0} = imm; } +def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, + IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm", + [/* For disassembly only; pattern left blank */]> { + bits<4> Rd; + bits<4> Rn; + bits<4> Rm; + let Inst{11-4} = 0b00000000; + let Inst{25} = 0; + let Inst{20} = 1; + let Inst{3-0} = Rm; + let Inst{15-12} = Rd; + let Inst{19-16} = Rn; +} def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift", [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> { diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 0f6aeb7052..0ff1e56fa4 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -130,3 +130,6 @@ # CHECK: msr cpsr_fc, r0 0x00 0xf0 0x29 0xe1 + +# CHECK: rsbs r6, r7, r8 +0x08 0x60 0x77 0xe0 |