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authorAndrew Lenharth <andrewl@lenharth.org>2006-08-17 16:07:50 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2006-08-17 16:07:50 +0000
commitd337295fb0f724d9da1e029260f68ef09b25e1fe (patch)
tree04a61414fe982c4dfbac63d91fe8b1e09bb98532
parentc63e56ee5f00da39563c174262872ec5e96a4bb5 (diff)
Add the 'c' constraint as needed by the linux kernel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29747 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp9
1 files changed, 7 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e1e3ef38f9..7a47959934 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4186,6 +4186,7 @@ X86TargetLowering::getConstraintType(char ConstraintLetter) const {
case 'Y':
case 'S':
case 'D':
+ case 'c':
return C_RegisterClass;
default: return TargetLowering::getConstraintType(ConstraintLetter);
}
@@ -4201,11 +4202,15 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
default: break; // Unknown constraint letter
case 'S': // ESI
if (VT == MVT::i32)
- return make_vector<unsigned>(X86::ESI,0);
+ return make_vector<unsigned>(X86::ESI,0);
break;
case 'D': // EDI
if (VT == MVT::i32)
- return make_vector<unsigned>(X86::EDI,0);
+ return make_vector<unsigned>(X86::EDI,0);
+ break;
+ case 'c': // ECX
+ if (VT == MVT::i32)
+ return make_vector<unsigned>(X86::ECX, 0);
break;
case 'A': // EAX/EDX
if (VT == MVT::i32 || VT == MVT::i64)