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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-19 19:51:03 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-19 19:51:03 +0000 |
| commit | d22170e16a42aed0212e1e52f189bfb8b7c7105d (patch) | |
| tree | cb8a00035e2e5aecd94210c5f4810f8cacceb13b | |
| parent | ee973147ac0aad6471f5506c3278654baec4d1c0 (diff) | |
ARM NEON two-operand aliases for VPADD.
rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 10 | ||||
| -rw-r--r-- | test/MC/ARM/neon-pairwise-encoding.s | 10 |
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index cac8f45468..ef987d2105 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5939,6 +5939,16 @@ def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm", def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm", (VMINfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; +// Two-operand variants for VPADD. +def : NEONInstAlias<"vpadd${p}.i8 $Vdn, $Vm", + (VPADDi8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vpadd${p}.i16 $Vdn, $Vm", + (VPADDi16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vpadd${p}.i32 $Vdn, $Vm", + (VPADDi32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; +def : NEONInstAlias<"vpadd${p}.f32 $Vdn, $Vm", + (VPADDf DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; + // 'gas' compatibility aliases for quad-word instructions. Strictly speaking, // these should restrict to just the Q register variants, but the register // classes are enough to match correctly regardless, so we keep it simple diff --git a/test/MC/ARM/neon-pairwise-encoding.s b/test/MC/ARM/neon-pairwise-encoding.s index 65c47bd64a..b1e86aa58e 100644 --- a/test/MC/ARM/neon-pairwise-encoding.s +++ b/test/MC/ARM/neon-pairwise-encoding.s @@ -8,6 +8,16 @@ vpadd.i32 d16, d17, d16 @ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] vpadd.f32 d16, d16, d17 + +@ CHECK: vpadd.i8 d17, d17, d16 @ encoding: [0xb0,0x1b,0x41,0xf2] + vpadd.i8 d17, d16 +@ CHECK: vpadd.i16 d17, d17, d16 @ encoding: [0xb0,0x1b,0x51,0xf2] + vpadd.i16 d17, d16 +@ CHECK: vpadd.i32 d17, d17, d16 @ encoding: [0xb0,0x1b,0x61,0xf2] + vpadd.i32 d17, d16 +@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xf3] + vpadd.f32 d16, d17 + @ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xf3] vpaddl.s8 d16, d16 @ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xf3] |