diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2012-12-25 17:22:53 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-12-25 17:22:53 +0000 |
| commit | cd9ea5198660a80c9c28c6471b0983bb450ca8cb (patch) | |
| tree | 970da7926be09c4e4a81f5ae9b47237cbdfefce6 | |
| parent | 59a65f7b24350cf483d777acfb403e9b8a31a771 (diff) | |
Expand PPC64 atomic load and store
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/atomic-2.ll | 20 |
2 files changed, 22 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9cc4e9615d..b14c181249 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -443,6 +443,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index a427379a8b..40b4a2eea9 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -24,3 +24,23 @@ define i64 @exchange(i64* %mem, i64 %val) nounwind { ; CHECK: stdcx. ret i64 %tmp } + +define void @atomic_store(i64* %mem, i64 %val) nounwind { +entry: +; CHECK: @atomic_store + store atomic i64 %val, i64* %mem release, align 64 +; CHECK: ldarx +; CHECK: stdcx. + ret void +} + +define i64 @atomic_load(i64* %mem) nounwind { +entry: +; CHECK: @atomic_load + %tmp = load atomic i64* %mem acquire, align 64 +; CHECK: ldarx +; CHECK: stdcx. +; CHECK: stdcx. + ret i64 %tmp +} + |