diff options
author | Bob Wilson <bob.wilson@apple.com> | 2009-10-08 18:52:56 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2009-10-08 18:52:56 +0000 |
commit | cd7e327cdf6f3b6171905dec615cc7bf3b24f1ac (patch) | |
tree | dc35061201bafa91a4d0329cf8ed728ac3a10ffa | |
parent | af4a891273b82798e97ad3e59359d93f3c8d6c19 (diff) |
Clean up some unnecessary initializations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83566 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index da4f037f26..0739d4731d 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1405,7 +1405,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { } // Quad registers are loaded with two separate instructions, where one // loads the even registers and the other loads the odd registers. - EVT RegVT = VT; + EVT RegVT; unsigned Opc2 = 0; switch (VT.getSimpleVT().SimpleTy) { default: llvm_unreachable("unhandled vld3 type"); @@ -1465,7 +1465,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { } // Quad registers are loaded with two separate instructions, where one // loads the even registers and the other loads the odd registers. - EVT RegVT = VT; + EVT RegVT; unsigned Opc2 = 0; switch (VT.getSimpleVT().SimpleTy) { default: llvm_unreachable("unhandled vld4 type"); |