diff options
author | Dan Gohman <gohman@apple.com> | 2009-01-03 19:22:06 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-01-03 19:22:06 +0000 |
commit | cc91d63ab7b3ee5c80497acf77f75ad9f76e985c (patch) | |
tree | 7f61a6ff6237b6950e307cb8e0a867edb7fec717 | |
parent | 1eb9268080498bc7b6d2d5df6fe8c13d6f939de0 (diff) |
Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61613 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/pr3250.ll | 17 |
2 files changed, 19 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4fb50e30db..f1e43a9024 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3277,6 +3277,8 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { // See if we can recursively simplify the LHS. unsigned Amt = RHSC->getZExtValue(); + // Watch out for shift count overflow though. + if (Amt >= Mask.getBitWidth()) break; APInt NewMask = Mask << Amt; SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); if (SimplifyLHS.getNode()) { diff --git a/test/CodeGen/X86/pr3250.ll b/test/CodeGen/X86/pr3250.ll new file mode 100644 index 0000000000..dce154f185 --- /dev/null +++ b/test/CodeGen/X86/pr3250.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR3250 + +declare i32 @safe_sub_func_short_u_u(i16 signext, i16 signext) nounwind + +define i32 @func_106(i32 %p_107) nounwind { +entry: + %0 = tail call i32 (...)* @safe_div_(i32 %p_107, i32 1) nounwind + ; <i32> [#uses=1] + %1 = lshr i32 %0, -9 ; <i32> [#uses=1] + %2 = trunc i32 %1 to i16 ; <i16> [#uses=1] + %3 = tail call i32 @safe_sub_func_short_u_u(i16 signext 1, i16 signext +%2) nounwind ; <i32> [#uses=0] + ret i32 undef +} + +declare i32 @safe_div_(...) |