diff options
| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-18 19:00:23 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-09-18 19:00:23 +0000 |
| commit | ca6f296b483e203b33a050fe52ebab2eae1541b0 (patch) | |
| tree | efbbd0f66c4160ca2603bbbfe2dcf9496477b426 | |
| parent | 354efd88db96c9662d41c1e154fdee37324802db (diff) | |
Fix typos in my prev commit, found by Tobi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140003 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index cc904d9a1d..a570cd1609 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -13445,7 +13445,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, ISD::LoadExtType Ext = Ld->getExtensionType(); - // If yhis is a vector EXT Load then attempt to optimize it using a + // If this is a vector EXT Load then attempt to optimize it using a // shuffle. We need SSE4 for the shuffles. // TODO: It is possible to support ZExt by zeroing the undef values // during the shuffle phase or after the shuffle. @@ -13457,7 +13457,7 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, unsigned RegSz = RegVT.getSizeInBits(); unsigned MemSz = MemVT.getSizeInBits(); assert(RegSz > MemSz && "Register size must be greater than the mem size"); - // All sized must be a power of two + // All sizes must be a power of two if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); // Attempt to load the original value using a single load op. |