Compute a backwards SubReg -> SubRegIndex map for each register.

This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 23 insertions, 0 deletions

diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 95394bdee0..145ec26c9e 100644
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -191,6 +191,9 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
     if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
       throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
                     " appears twice in Register " + getName());
+    // Map explicit sub-registers first, so the names take precedence.
+    // The inherited sub-registers are mapped below.
+    SubReg2Idx.insert(std::make_pair(SR, Idx));
   }
 
   // Keep track of inherited subregs and how they can be reached.
@@ -309,6 +312,19 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
         SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second;
   }
 
+  // Compute the inverse SubReg -> Idx map.
+  for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end();
+       SI != SE; ++SI) {
+    // Ignore idempotent sub-register indices.
+    if (SI->second == this)
+      continue;
+    // Is is possible to have multiple names for the same sub-register.
+    // For example, XMM0 appears as sub_xmm, sub_sd, and sub_ss in YMM0.
+    // Eventually, this degeneration should go away, but for now we simply give
+    // precedence to the explicit sub-register index over the inherited ones.
+    SubReg2Idx.insert(std::make_pair(SI->second, SI->first));
+  }
+
   // Initialize RegUnitList. A register with no subregisters creates its own
   // unit. Otherwise, it inherits all its subregister's units. Because
   // getSubRegs is called recursively, this processes the register hierarchy in
diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h
index b0f8f4683f..dce08b4ff5 100644
--- a/utils/TableGen/CodeGenRegisters.h
+++ b/utils/TableGen/CodeGenRegisters.h
@@ -113,6 +113,12 @@ namespace llvm {
     void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
                             CodeGenRegBank&) const;
 
+    // Return the sub-register index naming Reg as a sub-register of this
+    // register. Returns NULL if Reg is not a sub-register.
+    CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
+      return SubReg2Idx.lookup(Reg);
+    }
+
     // List of super-registers in topological order, small to large.
     typedef std::vector<const CodeGenRegister*> SuperRegList;
 
@@ -157,6 +163,7 @@ namespace llvm {
     bool SubRegsComplete;
     SubRegMap SubRegs;
     SuperRegList SuperRegs;
+    DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
     RegUnitList RegUnits;
   };