- Removing the infamous r2rMap_ and rep() method. Now the coalescer will update

register defs and uses after each successful coalescing.
- Also removed a number of hacks and fixed some subtle kill information bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47167 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 327 insertions, 402 deletions

diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h
index e7ebb5157d..532d814935 100644
--- a/include/llvm/CodeGen/LiveInterval.h
+++ b/include/llvm/CodeGen/LiveInterval.h
@@ -37,19 +37,18 @@ namespace llvm {
   /// merge point), it contains ~0u,x. If the value number is not in use, it
   /// contains ~1u,x to indicate that the value # is not used. 
   ///   def   - Instruction # of the definition.
-  ///   reg   - Source reg iff val# is defined by a copy; zero otherwise.
+  ///   copy  - Copy iff val# is defined by a copy; zero otherwise.
   ///   hasPHIKill - One or more of the kills are PHI nodes.
-  ///   kills - Instruction # of the kills. If a kill is an odd #, it means
-  ///           the kill is a phi join point.
+  ///   kills - Instruction # of the kills.
   struct VNInfo {
     unsigned id;
     unsigned def;
-    unsigned reg;
+    MachineInstr *copy;
     bool hasPHIKill;
     SmallVector<unsigned, 4> kills;
-    VNInfo() : id(~1U), def(~1U), reg(0), hasPHIKill(false) {}
-    VNInfo(unsigned i, unsigned d, unsigned r)
-      : id(i), def(d), reg(r), hasPHIKill(false) {}
+    VNInfo() : id(~1U), def(~1U), copy(0), hasPHIKill(false) {}
+    VNInfo(unsigned i, unsigned d, MachineInstr *c)
+      : id(i), def(d), copy(c), hasPHIKill(false) {}
   };
 
   /// LiveRange structure - This represents a simple register range in the
@@ -159,14 +158,14 @@ namespace llvm {
     /// another.
     void copyValNumInfo(VNInfo *DstValNo, const VNInfo *SrcValNo) {
       DstValNo->def = SrcValNo->def;
-      DstValNo->reg = SrcValNo->reg;
+      DstValNo->copy = SrcValNo->copy;
       DstValNo->hasPHIKill = SrcValNo->hasPHIKill;
       DstValNo->kills = SrcValNo->kills;
     }
 
     /// getNextValue - Create a new value number and return it.  MIIdx specifies
     /// the instruction that defines the value number.
-    VNInfo *getNextValue(unsigned MIIdx, unsigned SrcReg,
+    VNInfo *getNextValue(unsigned MIIdx, MachineInstr *CopyMI,
                          BumpPtrAllocator &VNInfoAllocator) {
 #ifdef __GNUC__
       unsigned Alignment = __alignof__(VNInfo);
@@ -176,7 +175,7 @@ namespace llvm {
 #endif
       VNInfo *VNI= static_cast<VNInfo*>(VNInfoAllocator.Allocate(sizeof(VNInfo),
                                                                  Alignment));
-      new (VNI) VNInfo(valnos.size(), MIIdx, SrcReg);
+      new (VNI) VNInfo(valnos.size(), MIIdx, CopyMI);
       valnos.push_back(VNI);
       return VNI;
     }
@@ -199,7 +198,7 @@ namespace llvm {
     void addKills(VNInfo *VNI, const SmallVector<unsigned, 4> &kills) {
       for (unsigned i = 0, e = kills.size(); i != e; ++i) {
         unsigned KillIdx = kills[i];
-        if (!liveAt(KillIdx)) {
+        if (!liveBeforeAndAt(KillIdx)) {
           SmallVector<unsigned, 4>::iterator
             I = std::lower_bound(VNI->kills.begin(), VNI->kills.end(), KillIdx);
           VNI->kills.insert(I, KillIdx);
@@ -230,6 +229,15 @@ namespace llvm {
         E = std::upper_bound(kills.begin(), kills.end(), End);
       kills.erase(I, E);
     }
+
+    /// isKill - Return true if the specified index is a kill of the
+    /// specified val#.
+    bool isKill(const VNInfo *VNI, unsigned KillIdx) const {
+      const SmallVector<unsigned, 4> &kills = VNI->kills;
+      SmallVector<unsigned, 4>::const_iterator
+        I = std::lower_bound(kills.begin(), kills.end(), KillIdx);
+      return I != kills.end() && *I == KillIdx;
+    }
     
     /// MergeValueNumberInto - This method is called when two value nubmers
     /// are found to be equivalent.  This eliminates V1, replacing all
@@ -284,6 +292,11 @@ namespace llvm {
 
     bool liveAt(unsigned index) const;
 
+    // liveBeforeAndAt - Check if the interval is live at the index and the
+    // index just before it. If index is liveAt, check if it starts a new live
+    // range.If it does, then check if the previous live range ends at index-1.
+    bool liveBeforeAndAt(unsigned index) const;
+
     /// getLiveRangeContaining - Return the live range that contains the
     /// specified index, or null if there is none.
     const LiveRange *getLiveRangeContaining(unsigned Idx) const {
diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index 1667ee3a75..440ae6ec5b 100644
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -229,6 +229,10 @@ namespace llvm {
 
     BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
 
+    /// getVNInfoSourceReg - Helper function that parses the specified VNInfo
+    /// copy field and returns the source register that defines it.
+    unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
+
     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
     virtual void releaseMemory();
 
@@ -276,7 +280,7 @@ namespace llvm {
                                    MachineBasicBlock::iterator mi,
                                    unsigned MIIdx,
                                    LiveInterval &interval,
-                                   unsigned SrcReg);
+                                   MachineInstr *CopyMI);
 
     /// handleLiveInRegister - Create interval for a livein register.
     void handleLiveInRegister(MachineBasicBlock* mbb,
diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp
index b09ffd48e6..741c35c43a 100644
--- a/lib/CodeGen/LiveInterval.cpp
+++ b/lib/CodeGen/LiveInterval.cpp
@@ -44,6 +44,27 @@ bool LiveInterval::liveAt(unsigned I) const {
   return r->contains(I);
 }
 
+// liveBeforeAndAt - Check if the interval is live at the index and the index
+// just before it. If index is liveAt, check if it starts a new live range.
+// If it does, then check if the previous live range ends at index-1.
+bool LiveInterval::liveBeforeAndAt(unsigned I) const {
+  Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
+
+  if (r == ranges.begin())
+    return false;
+
+  --r;
+  if (!r->contains(I))
+    return false;
+  if (I != r->start)
+    return true;
+  // I is the start of a live range. Check if the previous live range ends
+  // at I-1.
+  if (r == ranges.begin())
+    return false;
+  return r->end == I;
+}
+
 // overlaps - Return true if the intersection of the two live intervals is
 // not empty.
 //
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index d32fc62379..a64bf60f3b 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -224,14 +224,12 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
     // Get the Idx of the defining instructions.
     unsigned defIndex = getDefIndex(MIIdx);
     VNInfo *ValNo;
+    MachineInstr *CopyMI = NULL;
     unsigned SrcReg, DstReg;
-    if (tii_->isMoveInstr(*mi, SrcReg, DstReg))
-      ValNo = interval.getNextValue(defIndex, SrcReg, VNInfoAllocator);
-    else if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
-      ValNo = interval.getNextValue(defIndex, mi->getOperand(1).getReg(),
-                                    VNInfoAllocator);
-    else
-      ValNo = interval.getNextValue(defIndex, 0, VNInfoAllocator);
+    if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+        tii_->isMoveInstr(*mi, SrcReg, DstReg))
+      CopyMI = mi;
+    ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
 
     assert(ValNo->id == 0 && "First value in interval is not 0?");
 
@@ -326,13 +324,12 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
 
       // The new value number (#1) is defined by the instruction we claimed
       // defined value #0.
-      VNInfo *ValNo = interval.getNextValue(0, 0, VNInfoAllocator);
-      ValNo->def = OldValNo->def;
-      ValNo->reg = OldValNo->reg;
+      VNInfo *ValNo = interval.getNextValue(OldValNo->def, OldValNo->copy,
+                                            VNInfoAllocator);
       
       // Value#0 is now defined by the 2-addr instruction.
-      OldValNo->def = RedefIndex;
-      OldValNo->reg = 0;
+      OldValNo->def  = RedefIndex;
+      OldValNo->copy = 0;
       
       // Add the new live interval which replaces the range for the input copy.
       LiveRange LR(DefIndex, RedefIndex, ValNo);
@@ -364,7 +361,6 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
         DOUT << " Removing [" << Start << "," << End << "] from: ";
         interval.print(DOUT, tri_); DOUT << "\n";
         interval.removeRange(Start, End);
-        interval.addKill(VNI, Start);
         VNI->hasPHIKill = true;
         DOUT << " RESULT: "; interval.print(DOUT, tri_);
 
@@ -383,14 +379,12 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
       unsigned defIndex = getDefIndex(MIIdx);
       
       VNInfo *ValNo;
+      MachineInstr *CopyMI = NULL;
       unsigned SrcReg, DstReg;
-      if (tii_->isMoveInstr(*mi, SrcReg, DstReg))
-        ValNo = interval.getNextValue(defIndex, SrcReg, VNInfoAllocator);
-      else if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
-        ValNo = interval.getNextValue(defIndex, mi->getOperand(1).getReg(),
-                                      VNInfoAllocator);
-      else
-        ValNo = interval.getNextValue(defIndex, 0, VNInfoAllocator);
+      if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+          tii_->isMoveInstr(*mi, SrcReg, DstReg))
+        CopyMI = mi;
+      ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator);
       
       unsigned killIndex = getInstructionIndex(&mbb->back()) + InstrSlots::NUM;
       LiveRange LR(defIndex, killIndex, ValNo);
@@ -408,7 +402,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
                                               MachineBasicBlock::iterator mi,
                                               unsigned MIIdx,
                                               LiveInterval &interval,
-                                              unsigned SrcReg) {
+                                              MachineInstr *CopyMI) {
   // A physical register cannot be live across basic block, so its
   // lifetime must end somewhere in its defining basic block.
   DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
@@ -449,7 +443,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
   // The only case we should have a dead physreg here without a killing or
   // instruction where we know it's dead is if it is live-in to the function
   // and never used.
-  assert(!SrcReg && "physreg was not killed in defining block!");
+  assert(!CopyMI && "physreg was not killed in defining block!");
   end = getDefIndex(start) + 1;  // It's dead.
 
 exit:
@@ -458,7 +452,7 @@ exit:
   // Already exists? Extend old live interval.
   LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
   VNInfo *ValNo = (OldLR != interval.end())
-    ? OldLR->valno : interval.getNextValue(start, SrcReg, VNInfoAllocator);
+    ? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator);
   LiveRange LR(start, end, ValNo);
   interval.addRange(LR);
   interval.addKill(LR.valno, end);
@@ -472,12 +466,12 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
   if (TargetRegisterInfo::isVirtualRegister(reg))
     handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
   else if (allocatableRegs_[reg]) {
+    MachineInstr *CopyMI = NULL;
     unsigned SrcReg, DstReg;
-    if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
-      SrcReg = MI->getOperand(1).getReg();
-    else if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
-      SrcReg = 0;
-    handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
+    if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
+        tii_->isMoveInstr(*MI, SrcReg, DstReg))
+      CopyMI = MI;
+    handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), CopyMI);
     // Def of a register also defines its sub-registers.
     for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS)
       // Avoid processing some defs more than once.
@@ -601,6 +595,20 @@ LiveInterval LiveIntervals::createInterval(unsigned reg) {
   return LiveInterval(reg, Weight);
 }
 
+/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
+/// copy field and returns the source register that defines it.
+unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const {
+  if (!VNI->copy)
+    return 0;
+
+  if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
+    return VNI->copy->getOperand(1).getReg();
+  unsigned SrcReg, DstReg;
+  if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg))
+    return SrcReg;
+  assert(0 && "Unrecognized copy instruction!");
+  return 0;
+}
 
 //===----------------------------------------------------------------------===//
 // Register allocator hooks.
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 4734d22571..0c83933726 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -106,9 +106,8 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
   // Get the location that B is defined at.  Two options: either this value has
   // an unknown definition point or it is defined at CopyIdx.  If unknown, we 
   // can't process it.
-  if (!BValNo->reg) return false;
-  assert(BValNo->def == CopyIdx &&
-         "Copy doesn't define the value?");
+  if (!BValNo->copy) return false;
+  assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
   
   // AValNo is the value number in A that defines the copy, A3 in the example.
   LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
@@ -116,14 +115,14 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
   
   // If AValNo is defined as a copy from IntB, we can potentially process this.  
   // Get the instruction that defines this value number.
-  unsigned SrcReg = AValNo->reg;
+  unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
   if (!SrcReg) return false;  // Not defined by a copy.
     
   // If the value number is not defined by a copy instruction, ignore it.
-    
+
   // If the source register comes from an interval other than IntB, we can't
   // handle this.
-  if (rep(SrcReg) != IntB.reg) return false;
+  if (SrcReg != IntB.reg) return false;
   
   // Get the LiveRange in IntB that this value number starts with.
   LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
@@ -158,8 +157,8 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
   // We are about to delete CopyMI, so need to remove it as the 'instruction
   // that defines this value #'. Update the the valnum with the new defining
   // instruction #.
-  BValNo->def = FillerStart;
-  BValNo->reg = 0;
+  BValNo->def  = FillerStart;
+  BValNo->copy = NULL;
   
   // Okay, we can merge them.  We need to insert a new liverange:
   // [ValLR.end, BLR.begin) of either value number, then we merge the
@@ -223,7 +222,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
 
   unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
 
-  // BValNo is a value number in B that is defined by a copy from A.  'B3' in
+  // BValNo is a value number in B that is defined by a copy from A. 'B3' in
   // the example above.
   LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
   VNInfo *BValNo = BLR->valno;
@@ -231,7 +230,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
   // Get the location that B is defined at.  Two options: either this value has
   // an unknown definition point or it is defined at CopyIdx.  If unknown, we 
   // can't process it.
-  if (!BValNo->reg) return false;
+  if (!BValNo->copy) return false;
   assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
   
   // AValNo is the value number in A that defines the copy, A3 in the example.
@@ -243,35 +242,14 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
     return false;
   MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
   const TargetInstrDesc &TID = DefMI->getDesc();
-  if (!TID.isCommutable())
-    return false;
-  int Idx = -1;
-  for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = DefMI->getOperand(i);
-    if (!MO.isRegister()) continue;
-    unsigned Reg = MO.getReg();
-    if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
-      if (rep(Reg) == IntA.reg) {
-        // If the dest register comes from an interval other than IntA, we
-        // can't handle this.
-        if (Reg != IntA.reg)
-          return false;
-        continue;
-      }
-      if (Idx != -1)
-        // FIXME: Being overly careful here. We just need to figure out the
-        // which register operand will become the new def.
-        return false;
-      Idx = i;
-    }
-  }
-  if (Idx == -1)
-    // Something like %reg1024 = add %reg1024, %reg1024
+  unsigned NewDstIdx;
+  if (!TID.isCommutable() ||
+      !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
     return false;
 
-  MachineOperand &MO = DefMI->getOperand(Idx);
-  unsigned NewReg = MO.getReg();
-  if (rep(NewReg) != IntB.reg || !MO.isKill())
+  MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
+  unsigned NewReg = NewDstMO.getReg();
+  if (NewReg != IntB.reg || !NewDstMO.isKill())
     return false;
 
   // Make sure there are no other definitions of IntB that would reach the
@@ -329,16 +307,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
     unsigned SrcReg, DstReg;
     if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
       continue;
-    unsigned repDstReg = rep(DstReg);
-    if (repDstReg != IntB.reg) {
-      // Update dst register interval val# since its source register has
-      // changed.
-      LiveInterval &DLI = li_->getInterval(repDstReg);
-      LiveInterval::iterator DLR =
-        DLI.FindLiveRangeContaining(li_->getDefIndex(UseIdx));
-      DLR->valno->reg = NewReg;
-      ChangedCopies.insert(UseMI);
-    } else {
+    if (DstReg == IntB.reg) {
       // This copy will become a noop. If it's defining a new val#,
       // remove that val# as well. However this live range is being
       // extended to the end of the existing live range defined by the copy.
@@ -389,14 +358,23 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
   return true;
 }
 
-/// AddSubRegIdxPairs - Recursively mark all the registers represented by the
-/// specified register as sub-registers. The recursion level is expected to be
-/// shallow.
-void SimpleRegisterCoalescing::AddSubRegIdxPairs(unsigned Reg, unsigned SubIdx) {
-  std::vector<unsigned> &JoinedRegs = r2rRevMap_[Reg];
-  for (unsigned i = 0, e = JoinedRegs.size(); i != e; ++i) {
-    SubRegIdxes.push_back(std::make_pair(JoinedRegs[i], SubIdx));
-    AddSubRegIdxPairs(JoinedRegs[i], SubIdx);
+/// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
+/// due to live range lengthening as the result of coalescing.
+void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
+                                                      LiveInterval &LI) {
+  for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
+         UE = mri_->use_end(); UI != UE; ++UI) {
+    MachineOperand &UseMO = UI.getOperand();
+    if (UseMO.isKill()) {
+      MachineInstr *UseMI = UseMO.getParent();
+      unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
+      if (JoinedCopies.count(UseMI))
+        continue;
+      LiveInterval::const_iterator UI = LI.FindLiveRangeContaining(UseIdx);
+      assert(UI != LI.end());
+      if (!LI.isKill(UI->valno, UseIdx+1))
+        UseMO.setIsKill(false);
+    }
   }
 }
 
@@ -411,7 +389,6 @@ bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
   if (MBB != L->getLoopLatch())
     return false;
 
-  DstReg = rep(DstReg);
   LiveInterval &LI = li_->getInterval(DstReg);
   unsigned DefIdx = li_->getInstructionIndex(CopyMI);
   LiveInterval::const_iterator DstLR =
@@ -425,6 +402,42 @@ bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
   return false;
 }
 
+/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
+/// update the subregister number if it is not zero. If DstReg is a
+/// physical register and the existing subregister number of the def / use
+/// being updated is not zero, make sure to set it to the correct physical
+/// subregister.
+void
+SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
+                                            unsigned SubIdx) {
+  bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
+  if (DstIsPhys && SubIdx) {
+    // Figure out the real physical register we are updating with.
+    DstReg = tri_->getSubReg(DstReg, SubIdx);
+    SubIdx = 0;
+  }
+
+  for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
+         E = mri_->reg_end(); I != E; ) {
+    MachineOperand &O = I.getOperand();
+    ++I;
+    if (DstIsPhys) {
+      unsigned UseSubIdx = O.getSubReg();
+      unsigned UseDstReg = DstReg;
+      if (UseSubIdx)
+        UseDstReg = tri_->getSubReg(DstReg, UseSubIdx);
+      O.setReg(UseDstReg);
+      O.setSubReg(0);
+    } else {
+      unsigned OldSubIdx = O.getSubReg();
+      assert((!SubIdx || !OldSubIdx) && "Conflicting sub-register index!");
+      if (SubIdx)
+        O.setSubReg(SubIdx);
+      O.setReg(DstReg);
+    }
+  }
+}
+
 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
 /// which are the src/dst of the copy instruction CopyMI.  This returns true
 /// if the copy was successfully coalesced away. If it is not currently
@@ -439,35 +452,26 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
 
   DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
 
-  // Get representative registers.
-  unsigned SrcReg = TheCopy.SrcReg;
-  unsigned DstReg = TheCopy.DstReg;
-
-  // CopyMI has been modified due to commuting.
-  if (ChangedCopies.count(CopyMI)) {
-    if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
-        ;
-    else if (CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
-      DstReg = CopyMI->getOperand(0).getReg();
-      SrcReg = CopyMI->getOperand(1).getReg();
-    } else
-      assert(0 && "Unrecognized move instruction!");
-    TheCopy.SrcReg = SrcReg;
-    TheCopy.DstReg = DstReg;
-    ChangedCopies.erase(CopyMI);
+  unsigned SrcReg;
+  unsigned DstReg;
+  bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
+  unsigned SubIdx = 0;
+  if (isExtSubReg) {
+    DstReg = CopyMI->getOperand(0).getReg();
+    SrcReg = CopyMI->getOperand(1).getReg();
+  } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
+    assert(0 && "Unrecognized copy instruction!");
+    return false;
   }
 
-  unsigned repSrcReg = rep(SrcReg);
-  unsigned repDstReg = rep(DstReg);
-  
   // If they are already joined we continue.
-  if (repSrcReg == repDstReg) {
+  if (SrcReg == DstReg) {
     DOUT << "\tCopy already coalesced.\n";
     return false;  // Not coalescable.
   }
   
-  bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg);
-  bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg);
+  bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
+  bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
 
   // If they are both physical registers, we cannot join them.
   if (SrcIsPhys && DstIsPhys) {
@@ -476,31 +480,31 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
   }
   
   // We only join virtual registers with allocatable physical registers.
-  if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
+  if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
     DOUT << "\tSrc reg is unallocatable physreg.\n";
     return false;  // Not coalescable.
   }
-  if (DstIsPhys && !allocatableRegs_[repDstReg]) {
+  if (DstIsPhys && !allocatableRegs_[DstReg]) {
     DOUT << "\tDst reg is unallocatable physreg.\n";
     return false;  // Not coalescable.
   }
 
-  bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
   unsigned RealDstReg = 0;
   if (isExtSubReg) {
-    unsigned SubIdx = CopyMI->getOperand(2).getImm();
-    if (SrcIsPhys)
+    SubIdx = CopyMI->getOperand(2).getImm();
+    if (SrcIsPhys) {
       // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
       // coalesced with AX.
-      repSrcReg = tri_->getSubReg(repSrcReg, SubIdx);
-    else if (DstIsPhys) {
+      SrcReg = tri_->getSubReg(SrcReg, SubIdx);
+      SubIdx = 0;
+    } else if (DstIsPhys) {
       // If this is a extract_subreg where dst is a physical register, e.g.
       // cl = EXTRACT_SUBREG reg1024, 1
       // then create and update the actual physical register allocated to RHS.
-      const TargetRegisterClass *RC = mri_->getRegClass(repSrcReg);
-      for (const unsigned *SRs = tri_->getSuperRegisters(repDstReg);
+      const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
+      for (const unsigned *SRs = tri_->getSuperRegisters(DstReg);
            unsigned SR = *SRs; ++SRs) {
-        if (repDstReg == tri_->getSubReg(SR, SubIdx) &&
+        if (DstReg == tri_->getSubReg(SR, SubIdx) &&
             RC->contains(SR)) {
           RealDstReg = SR;
           break;
@@ -511,7 +515,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
       // For this type of EXTRACT_SUBREG, conservatively
       // check if the live interval of the source register interfere with the
       // actual super physical register we are trying to coalesce with.
-      LiveInterval &RHS = li_->getInterval(repSrcReg);
+      LiveInterval &RHS = li_->getInterval(SrcReg);
       if (li_->hasInterval(RealDstReg) &&
           RHS.overlaps(li_->getInterval(RealDstReg))) {
         DOUT << "Interfere with register ";
@@ -524,24 +528,32 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
           DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
           return false; // Not coalescable
         }
+      SubIdx = 0;
     } else {
-      unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM;
-      unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM;
-      const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repDstReg);
+      unsigned SrcSize= li_->getInterval(SrcReg).getSize() / InstrSlots::NUM;
+      unsigned DstSize= li_->getInterval(DstReg).getSize() / InstrSlots::NUM;
+      const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
       unsigned Threshold = allocatableRCRegs_[RC].count();
       // Be conservative. If both sides are virtual registers, do not coalesce
       // if this will cause a high use density interval to target a smaller set
       // of registers.
       if (DstSize > Threshold || SrcSize > Threshold) {
-        LiveVariables::VarInfo &svi = lv_->getVarInfo(repSrcReg);
-        LiveVariables::VarInfo &dvi = lv_->getVarInfo(repDstReg);
+        LiveVariables::VarInfo &svi = lv_->getVarInfo(SrcReg);
+        LiveVariables::VarInfo &dvi = lv_->getVarInfo(DstReg);
         if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) {
           Again = true;  // May be possible to coalesce later.
           return false;
         }
       }
     }
-  } else if (differingRegisterClasses(repSrcReg, repDstReg)) {
+  } else if (differingRegisterClasses(SrcReg, DstReg)) {
+    // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
+    // with another? If it's the resulting destination register, then
+    // the subidx must be propagated to uses (but only those defined
+    // by the EXTRACT_SUBREG). If it's being coalesced into another
+    // register, it should be safe because register is assumed to have
+    // the register class of the super-register.
+
     // If they are not of the same register class, we cannot join them.
     DOUT << "\tSrc/Dest are different register classes.\n";
     // Allow the coalescer to try again in case either side gets coalesced to
@@ -552,9 +564,9 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
     return false;
   }
   
-  LiveInterval &SrcInt = li_->getInterval(repSrcReg);
-  LiveInterval &DstInt = li_->getInterval(repDstReg);
-  assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
+  LiveInterval &SrcInt = li_->getInterval(SrcReg);
+  LiveInterval &DstInt = li_->getInterval(DstReg);
+  assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
          "Register mapping is horribly broken!");
 
   DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
@@ -580,19 +592,20 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
     if (SrcEnd > li_->getDefIndex(CopyIdx)) {
       isDead = false;
     } else {
-      MachineOperand *MOU;
-      MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
+      unsigned LastUseIdx;
+      MachineOperand *LastUse =
+        lastRegisterUse(SrcStart, CopyIdx, SrcReg, LastUseIdx);
       if (LastUse) {
         // Shorten the liveinterval to the end of last use.
-        MOU->setIsKill();
+        LastUse->setIsKill();
         isDead = false;
         isShorten = true;
-        RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse));
-        RemoveEnd   = SrcEnd;
+        RemoveStart = li_->getDefIndex(LastUseIdx);
+        RemoveEnd = SrcEnd;
       } else {
         MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
         if (SrcMI) {
-          MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
+          MachineOperand *mops = findDefOperand(SrcMI, SrcReg);
           if (mops)
             // A dead def should have a single cycle interval.
             ++RemoveStart;
@@ -607,9 +620,9 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
   // think twice about coalescing them!
   if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) {
     LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
-    unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
-    unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
-    const TargetRegisterClass *RC = mf_->getRegInfo().getRegClass(JoinVReg);
+    unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
+    unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
+    const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
     unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
     if (TheCopy.isBackEdge)
       Threshold *= 2; // Favors back edge copies.
@@ -638,15 +651,15 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
     if (isDead) {
       // Result of the copy is dead. Propagate this property.
       if (SrcStart == 0) {
-        assert(TargetRegisterInfo::isPhysicalRegister(repSrcReg) &&
+        assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
                "Live-in must be a physical register!");
         // Live-in to the function but dead. Remove it from entry live-in set.
         // JoinIntervals may end up swapping the two intervals.
-        mf_->begin()->removeLiveIn(repSrcReg);
+        mf_->begin()->removeLiveIn(SrcReg);
       } else {
         MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
         if (SrcMI) {
-          MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
+          MachineOperand *mops = findDefOperand(SrcMI, SrcReg);
           if (mops)
             mops->setIsDead();
         }
@@ -679,21 +692,21 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
   LiveInterval *ResSrcInt = &SrcInt;
   LiveInterval *ResDstInt = &DstInt;
   if (Swapped) {
-    std::swap(repSrcReg, repDstReg);
+    std::swap(SrcReg, DstReg);
     std::swap(ResSrcInt, ResDstInt);
   }
-  assert(TargetRegisterInfo::isVirtualRegister(repSrcReg) &&
+  assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
          "LiveInterval::join didn't work right!");
                                
   // If we're about to merge live ranges into a physical register live range,
   // we have to update any aliased register's live ranges to indicate that they
   // have clobbered values for this range.
-  if (TargetRegisterInfo::isPhysicalRegister(repDstReg)) {
+  if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
     // Unset unnecessary kills.
     if (!ResDstInt->containsOneValue()) {
       for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
              E = ResSrcInt->end(); I != E; ++I)
-        unsetRegisterKills(I->start, I->end, repDstReg);
+        unsetRegisterKills(I->start, I->end, DstReg);
     }
 
     // If this is a extract_subreg where dst is a physical register, e.g.
@@ -709,58 +722,52 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
         assert(DstLR != ResDstInt->end() && "Invalid joined interval!");
         const VNInfo *DstValNo = DstLR->valno;
         if (CopiedValNos.insert(DstValNo)) {
-          VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->reg,
+          VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->copy,
                                                   li_->getVNInfoAllocator());
           ValNo->hasPHIKill = DstValNo->hasPHIKill;
           RealDstInt.addKills(ValNo, DstValNo->kills);
           RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
         }
       }
-      repDstReg = RealDstReg;
+      DstReg = RealDstReg;
     }
 
     // Update the liveintervals of sub-registers.
-    for (const unsigned *AS = tri_->getSubRegisters(repDstReg); *AS; ++AS)
+    for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
       li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
                                                  li_->getVNInfoAllocator());
   } else {
     // Merge use info if the destination is a virtual register.
-    LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
-    LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
+    LiveVariables::VarInfo& dVI = lv_->getVarInfo(DstReg);
+    LiveVariables::VarInfo& sVI = lv_->getVarInfo(SrcReg);
     dVI.NumUses += sVI.NumUses;
   }
 
-  // Remember these liveintervals have been joined.
-  JoinedLIs.set(repSrcReg - TargetRegisterInfo::FirstVirtualRegister);
-  if (TargetRegisterInfo::isVirtualRegister(repDstReg))
-    JoinedLIs.set(repDstReg - TargetRegisterInfo::FirstVirtualRegister);
-
+  // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
+  // larger super-register.
   if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
     if (!Swapped) {
-      // Make sure we allocate the larger super-register.
       ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
-      std::swap(repSrcReg, repDstReg);
+      std::swap(SrcReg, DstReg);
       std::swap(ResSrcInt, ResDstInt);
     }
-    unsigned SubIdx = CopyMI->getOperand(2).getImm();
-    SubRegIdxes.push_back(std::make_pair(repSrcReg, SubIdx));
-    AddSubRegIdxPairs(repSrcReg, SubIdx);
   }
 
   if (NewHeuristic) {
+    // Add all copies that define val# in the source interval into the queue.
     for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
            e = ResSrcInt->vni_end(); i != e; ++i) {
       const VNInfo *vni = *i;
-      if (vni->def && vni->def != ~1U && vni->def != ~0U) {
-        MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
-        unsigned SrcReg, DstReg;
-        if (CopyMI &&
-            JoinedCopies.count(CopyMI) == 0 &&
-            tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
-          unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
-          JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth,
-                                  isBackEdgeCopy(CopyMI, DstReg)));
-        }
+      if (!vni->def || vni->def == ~1U || vni->def == ~0U)
+        continue;
+      MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
+      unsigned NewSrcReg, NewDstReg;
+