diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-21 00:31:10 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-21 00:31:10 +0000 |
| commit | c7541c49a9dbb88c0ffe4b74bc8065eb68585148 (patch) | |
| tree | 997ce780418f4e3176495d5042562ac688b9d50d | |
| parent | c79507a4dd0c64e3d96fee6c57d0b2e3d14f4b77 (diff) | |
Fix bug in zero-store peephole pattern reported in pr11615.
The patch and test case were originally written by Mans Rullgard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 12 | ||||
| -rw-r--r-- | test/CodeGen/Mips/swzero.ll | 19 |
2 files changed, 27 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index eb8b16b24b..e5d76c8599 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1022,10 +1022,14 @@ let Predicates = [IsN64] in { } // peepholes -def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>, - Requires<[NotN64]>; -def : Pat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>, - Requires<[IsN64]>; +let Predicates = [NotN64] in { + def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; + def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>; +} +let Predicates = [IsN64] in { + def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; + def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>; +} // brcond patterns multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, diff --git a/test/CodeGen/Mips/swzero.ll b/test/CodeGen/Mips/swzero.ll new file mode 100644 index 0000000000..da1e036eb9 --- /dev/null +++ b/test/CodeGen/Mips/swzero.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +%struct.unaligned = type <{ i32 }> + +define void @zero_u(%struct.unaligned* nocapture %p) nounwind { +entry: +; CHECK: usw $zero + %x = getelementptr inbounds %struct.unaligned* %p, i32 0, i32 0 + store i32 0, i32* %x, align 1 + ret void +} + +define void @zero_a(i32* nocapture %p) nounwind { +entry: +; CHECK: sw $zero + store i32 0, i32* %p, align 4 + ret void +} + |