Move files to new sparc directory

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@563 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 1839 insertions, 0 deletions

diff --git a/lib/Target/Makefile b/lib/Target/Makefile
new file mode 100644
index 0000000000..ebcd23a242
--- /dev/null
+++ b/lib/Target/Makefile
@@ -0,0 +1,5 @@
+LEVEL = ../..
+DIRS = Sparc
+
+include $(LEVEL)/Makefile.common
+
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
new file mode 100644
index 0000000000..df290d63e7
--- /dev/null
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -0,0 +1,1667 @@
+//===-- SparcInternals.h - Header file for Sparc backend ---------*- C++ -*--=//
+//
+// This file defines stuff that is to be private to the Sparc backend, but is 
+// shared among different portions of the backend.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef SPARC_INTERNALS_H
+#define SPARC_INTERNALS_H
+
+#include "llvm/CodeGen/Sparc.h"
+#include "SparcRegInfo.h"
+
+#include <sys/types.h>
+#include "llvm/Type.h"
+
+// OpCodeMask definitions for the Sparc V9
+// 
+const OpCodeMask	Immed		= 0x00002000; // immed or reg operand?
+const OpCodeMask	Annul		= 0x20000000; // annul delay instr?
+const OpCodeMask	PredictTaken	= 0x00080000; // predict branch taken?
+
+
+enum SparcInstrSchedClass {
+  SPARC_NONE,		/* Instructions with no scheduling restrictions */
+  SPARC_IEUN,		/* Integer class that can use IEU0 or IEU1 */
+  SPARC_IEU0,		/* Integer class IEU0 */
+  SPARC_IEU1,		/* Integer class IEU1 */
+  SPARC_FPM,		/* FP Multiply or Divide instructions */
+  SPARC_FPA,		/* All other FP instructions */	
+  SPARC_CTI,		/* Control-transfer instructions */
+  SPARC_LD,		/* Load instructions */
+  SPARC_ST,		/* Store instructions */
+  SPARC_SINGLE,		/* Instructions that must issue by themselves */
+  
+  SPARC_INV,		/* This should stay at the end for the next value */
+  SPARC_NUM_SCHED_CLASSES = SPARC_INV
+};
+
+// inline operator int (const SparcInstrSchedClass& si) {
+//   return (int) si;
+// }
+// 
+// inline operator SparcInstrSchedClass (int i) {
+//   return (SparcInstrSchedClass) si;
+// }
+// 
+// inline operator const SparcInstrSchedClass (int i) {
+//   return (const SparcInstrSchedClass) si;
+// }
+
+//---------------------------------------------------------------------------
+// enum SparcMachineOpCode. 
+// const MachineInstrDescriptor SparcMachineInstrDesc[]
+// 
+// Purpose:
+//   Description of UltraSparc machine instructions.
+// 
+//---------------------------------------------------------------------------
+
+
+enum SparcMachineOpCode {
+
+  NOP,
+  
+  // Synthetic SPARC assembly opcodes for setting a register to a constant
+  SETSW,
+  SETUW,
+  
+  // Set high-order bits of register and clear low-order bits
+  SETHI,
+  
+  // Add or add with carry.
+  // Immed bit specifies if second operand is immediate(1) or register(0)
+  ADD,
+  ADDcc,
+  ADDC,
+  ADDCcc,
+
+  // Subtract or subtract with carry.
+  // Immed bit specifies if second operand is immediate(1) or register(0)
+  SUB,
+  SUBcc,
+  SUBC,
+  SUBCcc,
+  
+  // Integer multiply, signed divide, unsigned divide.
+  // Note that the deprecated 32-bit multiply and multiply-step are not used.
+  MULX,
+  SDIVX,
+  UDIVX,
+  
+  // Floating point add, subtract, compare
+  FADDS,
+  FADDD,
+  FADDQ,
+  FSUBS,
+  FSUBD,
+  FSUBQ,
+  FCMPS,
+  FCMPD,
+  FCMPQ,
+  // NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
+  
+  // Floating point multiply or divide.
+  FMULS,
+  FMULD,
+  FMULQ,
+  FSMULD,
+  FDMULQ,
+  FDIVS,
+  FDIVD,
+  FDIVQ,
+  FSQRTS,
+  FSQRTD,
+  FSQRTQ,
+  
+  // Logical operations
+  AND,
+  ANDcc,
+  ANDN,
+  ANDNcc,
+  OR,
+  ORcc,
+  ORN,
+  ORNcc,
+  XOR,
+  XORcc,
+  XNOR,
+  XNORcc,
+  
+  // Shift operations
+  SLL,
+  SRL,
+  SRA,
+  SLLX,
+  SRLX,
+  SRAX,
+  
+  // Floating point move, negate, and abs instructions
+  FMOVS,
+  FMOVD,
+//FMOVQ,
+  FNEGS,
+  FNEGD,
+//FNEGQ,
+  FABSS,
+  FABSD,
+//FABSQ,
+  
+  // Convert from floating point to floating point formats
+  FSTOD,
+  FSTOQ,
+  FDTOS,
+  FDTOQ,
+  FQTOS,
+  FQTOD,
+  
+  // Convert from floating point to integer formats
+  FSTOX,
+  FDTOX,
+  FQTOX,
+  FSTOI,
+  FDTOI,
+  FQTOI,
+  
+  // Convert from integer to floating point formats
+  FXTOS,
+  FXTOD,
+  FXTOQ,
+  FITOS,
+  FITOD,
+  FITOQ,
+  
+  // Branch on integer comparison with zero.
+  // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
+  // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
+  BRZ,
+  BRLEZ,
+  BRLZ,
+  BRNZ,
+  BRGZ,
+  BRGEZ,
+
+  // Branch on integer condition code.
+  // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
+  // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
+  BA,
+  BN,
+  BNE,
+  BE,
+  BG,
+  BLE,
+  BGE,
+  BL,
+  BGU,
+  BLEU,
+  BCC,
+  BCS,
+  BPOS,
+  BNEG,
+  BVC,
+  BVS,
+
+  // Branch on floating point condition code.
+  // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
+  // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
+  FBA,
+  FBN,
+  FBU,
+  FBG,
+  FBUG,
+  FBL,
+  FBUL,
+  FBLG,
+  FBNE,
+  FBE,
+  FBUE,
+  FBGE,
+  FBUGE,
+  FBLE,
+  FBULE,
+  FBO,
+
+  // Conditional move on integer comparison with zero.
+  MOVRZ,
+  MOVRLEZ,
+  MOVRLZ,
+  MOVRNZ,
+  MOVRGZ,
+  MOVRGEZ,
+
+  // Conditional move on integer condition code.
+  MOVA,
+  MOVN,
+  MOVNE,
+  MOVE,
+  MOVG,
+  MOVLE,
+  MOVGE,
+  MOVL,
+  MOVGU,
+  MOVLEU,
+  MOVCC,
+  MOVCS,
+  MOVPOS,
+  MOVNEG,
+  MOVVC,
+  MOVVS,
+
+  // Conditional move on floating point condition code.
+  // Note that the enum name is not the same as the assembly mnemonic below
+  // because that would duplicate some entries with those above.
+  // Therefore, we use MOVF here instead of MOV.
+  MOVFA,
+  MOVFN,
+  MOVFU,
+  MOVFG,
+  MOVFUG,
+  MOVFL,
+  MOVFUL,
+  MOVFLG,
+  MOVFNE,
+  MOVFE,
+  MOVFUE,
+  MOVFGE,
+  MOVFUGE,
+  MOVFLE,
+  MOVFULE,
+  MOVFO,
+
+  // Conditional move of floating point register on each of the above:
+  // i.   on integer comparison with zero.
+  // ii.  on integer condition code
+  // iii. on floating point condition code
+  // Note that the same set is repeated for S,D,Q register classes.
+  FMOVRSZ,
+  FMOVRSLEZ,
+  FMOVRSLZ,
+  FMOVRSNZ,
+  FMOVRSGZ,
+  FMOVRSGEZ,
+
+  FMOVSA,
+  FMOVSN,
+  FMOVSNE,
+  FMOVSE,
+  FMOVSG,
+  FMOVSLE,
+  FMOVSGE,
+  FMOVSL,
+  FMOVSGU,
+  FMOVSLEU,
+  FMOVSCC,
+  FMOVSCS,
+  FMOVSPOS,
+  FMOVSNEG,
+  FMOVSVC,
+  FMOVSVS,
+
+  FMOVSFA,
+  FMOVSFN,
+  FMOVSFU,
+  FMOVSFG,
+  FMOVSFUG,
+  FMOVSFL,
+  FMOVSFUL,
+  FMOVSFLG,
+  FMOVSFNE,
+  FMOVSFE,
+  FMOVSFUE,
+  FMOVSFGE,
+  FMOVSFUGE,
+  FMOVSFLE,
+  FMOVSFULE,
+  FMOVSFO,
+  
+  FMOVRDZ,
+  FMOVRDLEZ,
+  FMOVRDLZ,
+  FMOVRDNZ,
+  FMOVRDGZ,
+  FMOVRDGEZ,
+
+  FMOVDA,
+  FMOVDN,
+  FMOVDNE,
+  FMOVDE,
+  FMOVDG,
+  FMOVDLE,
+  FMOVDGE,
+  FMOVDL,
+  FMOVDGU,
+  FMOVDLEU,
+  FMOVDCC,
+  FMOVDCS,
+  FMOVDPOS,
+  FMOVDNEG,
+  FMOVDVC,
+  FMOVDVS,
+
+  FMOVDFA,
+  FMOVDFN,
+  FMOVDFU,
+  FMOVDFG,
+  FMOVDFUG,
+  FMOVDFL,
+  FMOVDFUL,
+  FMOVDFLG,
+  FMOVDFNE,
+  FMOVDFE,
+  FMOVDFUE,
+  FMOVDFGE,
+  FMOVDFUGE,
+  FMOVDFLE,
+  FMOVDFULE,
+  FMOVDFO,
+  
+  FMOVRQZ,
+  FMOVRQLEZ,
+  FMOVRQLZ,
+  FMOVRQNZ,
+  FMOVRQGZ,
+  FMOVRQGEZ,
+
+  FMOVQA,
+  FMOVQN,
+  FMOVQNE,
+  FMOVQE,
+  FMOVQG,
+  FMOVQLE,
+  FMOVQGE,
+  FMOVQL,
+  FMOVQGU,
+  FMOVQLEU,
+  FMOVQCC,
+  FMOVQCS,
+  FMOVQPOS,
+  FMOVQNEG,
+  FMOVQVC,
+  FMOVQVS,
+
+  FMOVQFA,
+  FMOVQFN,
+  FMOVQFU,
+  FMOVQFG,
+  FMOVQFUG,
+  FMOVQFL,
+  FMOVQFUL,
+  FMOVQFLG,
+  FMOVQFNE,
+  FMOVQFE,
+  FMOVQFUE,
+  FMOVQFGE,
+  FMOVQFUGE,
+  FMOVQFLE,
+  FMOVQFULE,
+  FMOVQFO,
+  
+  // Load integer instructions
+  LDSB,
+  LDSH,
+  LDSW,
+  LDUB,
+  LDUH,
+  LDUW,
+  LDX,
+  
+  // Load floating-point instructions
+  LD,
+  LDD,			// use of this for integers is deprecated for Sparc V9
+  LDQ,
+  
+  // Store integer instructions
+  STB,
+  STH,
+  STW,
+  STX,
+  
+  // Store floating-point instructions
+  ST,
+  STD,
+  
+  // Call, Return, and "Jump and link"
+  // Immed bit specifies if second operand is immediate(1) or register(0)
+  CALL,
+  JMPL,
+  RETURN,				// last valid opcode
+
+  // Synthetic phi operation for near-SSA form of machine code
+  PHI,
+  
+  // End-of-array marker
+  INVALID_OPCODE,
+  NUM_REAL_OPCODES = RETURN+1,		// number of valid opcodes
+  NUM_TOTAL_OPCODES = INVALID_OPCODE
+};
+
+const MachineInstrDescriptor SparcMachineInstrDesc[] = {
+  
+  // Fields of each structure:
+  // opCodeString,
+  //           numOperands,
+  //                resultPosition (0-based; -1 if no result),
+  //                     maxImmedConst,
+  //                         immedIsSignExtended,
+  //                                numDelaySlots (in cycles)
+  //					latency (in cycles)
+  //					    instr sched class (defined above)
+  //						instr class flags (defined in TargretMachine.h)
+  
+  { "NOP",	0,  -1,  0,  false, 0,	1,  SPARC_NONE,  M_NOP_FLAG },
+  
+  // Synthetic SPARC assembly opcodes for setting a register to a constant.
+  // Max immediate constant should be ignored for both these instructions.
+  { "SETSW",	2,   1,  0,  true,  0,  1,  SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "SETUW",	2,   1,  0,  false, 0,  1,  SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG },
+
+  // Set high-order bits of register and clear low-order bits
+  { "SETHI",	2,  1,  (1 << 22) - 1, false, 0,  1,  SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG },
+  
+  // Add or add with carry.
+  { "ADD",	3,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "ADDcc",	4,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG },
+  { "ADDC",	3,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "ADDCcc",	4,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG },
+
+  // Sub tract or subtract with carry.
+  { "SUB",	3,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "SUBcc",	4,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG },
+  { "SUBC",	3,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "SUBCcc",	4,  2,  (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG },
+
+  // Integer multiply, signed divide, unsigned divide.
+  // Note that the deprecated 32-bit multiply and multiply-step are not used.
+  { "MULX",	3,  2,  (1 << 12) - 1, true, 0, 3, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "SDIVX",	3,  2,  (1 << 12) - 1, true, 0, 6, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  { "UDIVX",	3,  2,  (1 << 12) - 1, true, 0, 6, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG },
+  
+  // Floating point add, subtract, compare.
+  // Note that destination of FCMP* instructions is operand 0, not operand 2.
+  { "FADDS",	3,  2,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FADDD",	3,  2,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FADDQ",	3,  2,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSUBS",	3,  2,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSUBD",	3,  2,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSUBQ",	3,  2,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FCMPS",	3,  0,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FCMPD",	3,  0,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FCMPQ",	3,  0,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  // NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
+  
+  // Floating point multiply or divide.
+  { "FMULS",	3,  2,  0,  false, 0, 3,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FMULD",	3,  2,  0,  false, 0, 3,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FMULQ",	3,  2,  0,  false, 0, 0,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSMULD",	3,  2,  0,  false, 0, 3,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FDMULQ",	3,  2,  0,  false, 0, 0,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FDIVS",	3,  2,  0,  false, 0, 12, SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FDIVD",	3,  2,  0,  false, 0, 22, SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FDIVQ",	3,  2,  0,  false, 0, 0,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSQRTS",	3,  2,  0,  false, 0, 12, SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSQRTD",	3,  2,  0,  false, 0, 22, SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSQRTQ",	3,  2,  0,  false, 0, 0,  SPARC_FPM,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  
+  // Logical operations
+  { "AND",	3,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "ANDcc",	4,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "ANDN",	3,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "ANDNcc",	4,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "OR",	3,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "ORcc",	4,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "ORN",	3,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "ORNcc",	4,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "XOR",	3,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "XORcc",	4,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "XNOR",	3,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "XNORcc",	4,  2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1,  M_INT_FLAG | M_LOGICAL_FLAG},
+  
+  // Shift operations
+  { "SLL",	3,  2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "SRL",	3,  2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "SRA",	3,  2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG },
+  { "SLLX",	3,  2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "SRLX",	3,  2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0,  M_INT_FLAG | M_LOGICAL_FLAG},
+  { "SRAX",	3,  2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0,  M_INT_FLAG | M_ARITH_FLAG },
+  
+  // Floating point move, negate, and abs instructions
+  { "FMOVS",	2,  1,  0,  false,  0,  1,  SPARC_FPA,  M_FLOAT_FLAG },
+  { "FMOVD",	2,  1,  0,  false,  0,  1,  SPARC_FPA,  M_FLOAT_FLAG },
+//{ "FMOVQ",	2,  1,  0,  false,  0,  ?,  SPARC_FPA,  M_FLOAT_FLAG },
+  { "FNEGS",	2,  1,  0,  false,  0,  1,  SPARC_FPA,  M_FLOAT_FLAG },
+  { "FNEGD",	2,  1,  0,  false,  0,  1,  SPARC_FPA,  M_FLOAT_FLAG },
+//{ "FNEGQ",	2,  1,  0,  false,  0,  ?,  SPARC_FPA,  M_FLOAT_FLAG },
+  { "FABSS",	2,  1,  0,  false,  0,  1,  SPARC_FPA,  M_FLOAT_FLAG },
+  { "FABSD",	2,  1,  0,  false,  0,  1,  SPARC_FPA,  M_FLOAT_FLAG },
+//{ "FABSQ",	2,  1,  0,  false,  0,  ?,  SPARC_FPA,  M_FLOAT_FLAG },
+  
+  // Convert from floating point to floating point formats
+  { "FSTOD",	2,  1,  0,  false,  0,  3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FSTOQ",	2,  1,  0,  false,  0,  0,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FDTOS",	2,  1,  0,  false,  0,  3,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FDTOQ",	2,  1,  0,  false,  0,  0,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FQTOS",	2,  1,  0,  false,  0,  0,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  { "FQTOD",	2,  1,  0,  false,  0,  0,  SPARC_FPA,  M_FLOAT_FLAG | M_ARITH_FLAG },
+  
+  // Convert from floating point to integer formats.
+  // Note that this accesses both integer and floating point registers.
+  { "FSTOX",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FDTOX",	2,  1,  0,  false, 0, 0,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FQTOX",	2,  1,  0,  false, 0, 2,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FSTOI",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FDTOI",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FQTOI",	2,  1,  0,  false, 0, 0,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  
+  // Convert from integer to floating point formats
+  // Note that this accesses both integer and floating point registers.
+  { "FXTOS",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FXTOD",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FXTOQ",	2,  1,  0,  false, 0, 0,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FITOS",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FITOD",	2,  1,  0,  false, 0, 3,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  { "FITOQ",	2,  1,  0,  false, 0, 0,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
+  
+  // Branch on integer comparison with zero.
+  // Latency includes the delay slot.
+  { "BRZ",	2, -1, (1 << 15) - 1, true, 1, 2,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG },
+  { "BRLEZ",	2, -1, (1 << 15) - 1, true, 1, 2,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG },
+  { "BRLZ",	2, -1, (1 << 15) - 1, true, 1, 2,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG },
+  { "BRNZ",	2, -1, (1 << 15) - 1, true, 1, 2,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG },
+  { "BRGZ",	2, -1, (1 << 15) - 1, true, 1, 2,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG },
+  { "BRGEZ",	2, -1, (1 << 15) - 1, true, 1, 2,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG },
+
+  // Branch on condition code.
+  // The first argument specifies the ICC register: %icc or %xcc
+  // Latency includes the delay slot.
+  { "BA",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BN",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BNE",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BE",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BG",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BLE",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BGE",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BL",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BGU",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BLEU",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BCC",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BCS",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BPOS",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BNEG",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BVC",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "BVS",	2,  -1, (1 << 21) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+
+  // Branch on floating point condition code.
+  // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
+  // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
+  // The first argument is the FCCn register (0 <= n <= 3).
+  // Latency includes the delay slot.
+  { "FBA",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBN",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBU",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBG",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBUG",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBL",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBUL",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBLG",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBNE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBUE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBGE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBUGE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBLE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBULE",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+  { "FBO",	2,  -1, (1 << 18) - 1, true, 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG },
+
+  // Conditional move on integer comparison with zero.
+  { "MOVRZ",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG },
+  { "MOVRLEZ",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG },
+  { "MOVRLZ",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG },
+  { "MOVRNZ",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG },
+  { "MOVRGZ",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG },
+  { "MOVRGEZ",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_INT_FLAG },
+
+  // Conditional move on integer condition code.
+  // The first argument specifies the ICC register: %icc or %xcc
+  { "MOVA",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVN",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVNE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVG",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVLE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVGE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVL",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVGU",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVLEU",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVCC",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVCS",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVPOS",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVNEG",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVVC",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVVS",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+
+  // Conditional move (of integer register) on floating point condition code.
+  // The first argument is the FCCn register (0 <= n <= 3).
+  // Note that the enum name above is not the same as the assembly mnemonic
+  // because some of the assembly mnemonics are the same as the move on
+  // integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
+  { "MOVA",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVN",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVU",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVG",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVUG",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVL",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVUL",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVLG",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVNE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVUE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVGE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVUGE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVLE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVULE",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+  { "MOVO",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_INT_FLAG },
+
+  // Conditional move of floating point register on each of the above:
+  // i.   on integer comparison with zero.
+  // ii.  on integer condition code
+  // iii. on floating point condition code
+  // Note that the same set is repeated for S,D,Q register classes.
+  { "FMOVRSZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRSLEZ",3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRSLZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRSNZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRSGZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRSGEZ",3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+
+  { "FMOVSA",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSN",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSNE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSLE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSGU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSLEU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSCC",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSCS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSPOS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSNEG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSVC",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSVS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+
+  { "FMOVSA",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSN",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSUG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSUL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSLG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSNE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSUE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSUGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSLE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSULE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVSO",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+
+  { "FMOVRDZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRDLEZ",3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRDLZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRDNZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRDGZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRDGEZ",3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+
+  { "FMOVDA",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDN",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDNE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDLE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDGU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDLEU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDCC",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDCS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDPOS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDNEG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDVC",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDVS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+
+  { "FMOVDA",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDN",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDUG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDUL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDLG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDNE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDUE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDUGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDLE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDULE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVDO",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+
+  { "FMOVRQZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRQLEZ",3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRQLZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRQNZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRQGZ",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+  { "FMOVRQGEZ",3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
+
+  { "FMOVQA",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQN",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQNE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQLE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQGU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQLEU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQCC",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQCS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQPOS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQNEG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQVC",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQVS",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+
+  { "FMOVQA",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQN",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQU",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQUG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQUL",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQLG",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQNE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQUE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQUGE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQLE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQULE",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  { "FMOVQO",	3,  2, 0,  false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG | M_FLOAT_FLAG },
+  
+  // Load integer instructions
+  // Latency includes 1 cycle for address generation (Sparc IIi)
+  // Signed loads of less than 64 bits need an extra cycle for sign-extension.
+  //
+  // Not reflected here: After a 3-cycle loads, all subsequent consecutive
+  // loads also require 3 cycles to avoid contention for the load return
+  // stage.  Latency returns to 2 cycles after the first cycle with no load.
+  { "LDSB",	3,  2, (1 << 12) - 1,  true, 0, 3,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  { "LDSH",	3,  2, (1 << 12) - 1,  true, 0, 3,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  { "LDSW",	3,  2, (1 << 12) - 1,  true, 0, 3,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  { "LDUB",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  { "LDUH",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  { "LDUW",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  { "LDX",	3,  2, (1 << 12) - 1,  true, 0, 2,  SPARC_LD,  M_INT_FLAG | M_LOAD_FLAG },
+  
+  // Load floating-point instructions
+  // Latency includes 1 cycle for address generation (Sparc IIi)
+  { "LD",	3, 2, (1 << 12) - 1, true, 0, 2,  SPARC_LD,  M_FLOAT_FLAG | M_LOAD_FLAG },
+  { "LDD",	3, 2, (1 << 12) - 1, true, 0, 2,  SPARC_LD,  M_FLOAT_FLAG | M_LOAD_FLAG },
+  { "LDQ",	3, 2, (1 << 12) - 1, true, 0, 2,  SPARC_LD,  M_FLOAT_FLAG | M_LOAD_FLAG },
+  
+  // Store integer instructions
+  // Latency includes 1 cycle for address generation (Sparc IIi)
+  { "STB",	3, -1, (1 << 12) - 1, true, 0, 2,  SPARC_ST,  M_INT_FLAG | M_STORE_FLAG },
+  { "STH",	3, -1, (1 << 12) - 1, true, 0, 2,  SPARC_ST,  M_INT_FLAG | M_STORE_FLAG },
+  { "STW",	3, -1, (1 << 12) - 1, true, 0, 2,  SPARC_ST,  M_INT_FLAG | M_STORE_FLAG },
+  { "STX",	3, -1, (1 << 12) - 1, true, 0, 3,  SPARC_ST,  M_INT_FLAG | M_STORE_FLAG },
+  
+  // Store floating-point instructions (Sparc IIi)
+  { "ST",	3, -1, (1 << 12) - 1, true, 0, 2,  SPARC_ST,  M_FLOAT_FLAG | M_STORE_FLAG},
+  { "STD",	3, -1, (1 << 12) - 1, true, 0, 2,  SPARC_ST,  M_FLOAT_FLAG | M_STORE_FLAG},
+  
+  // Call, Return and "Jump and link".
+  // Latency includes the delay slot.
+  { "CALL",	1, -1, (1 << 29) - 1, true, 1, 2,  SPARC_CTI,  M_BRANCH_FLAG | M_CALL_FLAG},
+  { "JMPL",	3, -1, (1 << 12) - 1, true, 1, 2,  SPARC_CTI,  M_BRANCH_FLAG | M_CALL_FLAG},
+  { "RETURN",	2, -1,  0,           false, 1, 2,  SPARC_CTI,  M_BRANCH_FLAG | M_RET_FLAG },
+  
+  // Synthetic phi operation for near-SSA form of machine code
+  // Number of operands is variable, indicated by -1.  Result is the first op.
+
+  { "PHI",	-1,  0,  0,  false, 0, 0, SPARC_INV,  M_DUMMY_PHI_FLAG },
+
+};
+
+
+
+//---------------------------------------------------------------------------
+// class UltraSparcInstrInfo 
+// 
+//