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authorRafael Espindola <rafael.espindola@gmail.com>2006-05-25 11:00:18 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-05-25 11:00:18 +0000
commitc3c1a86aa0fe3ccda2de383330b90b77aaccd710 (patch)
treee5b0c9fcfab35d0b2df079244247d4008d5e8d89
parent2776bd1d2a66854803b78a6a1ccfc3b9932b49b6 (diff)
port the ARM backend to use ISD::CALL instead of LowerCallTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28469 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp15
1 files changed, 3 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index e4e99db391..54c7101e40 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -40,13 +40,6 @@ namespace {
public:
ARMTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
-
- virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
- unsigned CC,
- bool isTailCall, SDOperand Callee, ArgListTy &Args,
- SelectionDAG &DAG);
-
};
}
@@ -56,11 +49,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::RET, MVT::Other, Custom);
}
-std::pair<SDOperand, SDOperand>
-ARMTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
- bool isVarArg, unsigned CC,
- bool isTailCall, SDOperand Callee,
- ArgListTy &Args, SelectionDAG &DAG) {
+static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
assert(0 && "Not implemented");
abort();
}
@@ -127,6 +116,8 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
abort();
case ISD::FORMAL_ARGUMENTS:
return LowerFORMAL_ARGUMENTS(Op, DAG);
+ case ISD::CALL:
+ return LowerCALL(Op, DAG);
case ISD::RET:
return LowerRET(Op, DAG);
}