Also add super- register class info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28222 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 2 deletions

diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index c9d604f082..0cac31bb36 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -49,15 +49,18 @@ public:
   typedef const MVT::ValueType* vt_iterator;
   typedef const TargetRegisterClass** sc_iterator;
 private:
+  bool  isSubClass;
   const vt_iterator VTs;
   const sc_iterator SubClasses;
+  const sc_iterator SuperClasses;
   const unsigned RegSize, Alignment;    // Size & Alignment of register in bytes
   const iterator RegsBegin, RegsEnd;
 public:
   TargetRegisterClass(const MVT::ValueType *vts,
-                      const TargetRegisterClass **scs,
+                      const TargetRegisterClass **subcs,
+                      const TargetRegisterClass **supcs,
                       unsigned RS, unsigned Al, iterator RB, iterator RE)
-    : VTs(vts), SubClasses(scs),
+    : VTs(vts), SubClasses(subcs), SuperClasses(supcs),
     RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
   virtual ~TargetRegisterClass() {}     // Allow subclasses
 
@@ -124,6 +127,27 @@ public:
     return I;
   }
   
+  /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
+  /// super-register class of this TargetRegisterClass.
+  bool hasSuperRegClass(const TargetRegisterClass *cs) const {
+    for (int i = 0; SuperClasses[i] != NULL; ++i) 
+      if (SuperClasses[i] == cs)
+        return true;
+    return false;
+  }
+
+  /// superclasses_begin / superclasses_end - Loop over all of the super-classes
+  /// of this register class.
+  sc_iterator superclasses_begin() const {
+    return SuperClasses;
+  }
+  
+  sc_iterator superclasses_end() const {
+    sc_iterator I = SuperClasses;
+    while (*I != NULL) ++I;
+    return I;
+  }
+  
   /// allocation_order_begin/end - These methods define a range of registers
   /// which specify the registers in this class that are valid to register
   /// allocate, and the preferred order to allocate them in.  For example,