diff options
| author | Bill Wendling <isanbard@gmail.com> | 2011-10-19 09:04:11 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-10-19 09:04:11 +0000 |
| commit | b677a135acb2fc5dabb94d8f7fd0839e43dea092 (patch) | |
| tree | 4fab5c8c1099e2e0c43ac6056a7cd70728e0e431 | |
| parent | 783993e79502641d4f2ec82f3db78320b6837f4e (diff) | |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142484 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 90c8f9c442..48dc4f29f4 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5905,12 +5905,6 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { .addReg(VReg2)); } - unsigned NewVReg2 = MRI->createVirtualRegister(TRC); - AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), NewVReg2) - .addImm(LPadList.size())); - AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) - .addReg(NewVReg1) - .addReg(NewVReg2)); BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) .addMBB(TrapBB) .addImm(ARMCC::HI) |