treat TAILCALL nodes identically to CALL nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21977 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 14 insertions, 4 deletions

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 28930cefb4..d7dab5d0a5 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1193,7 +1193,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
 
-  if (N.getOpcode() != ISD::CALL)
+  if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
     Reg = Result = (N.getValueType() != MVT::Other) ?
       MakeReg(N.getValueType()) : notIn;
   else {
@@ -1217,7 +1217,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
         (N.getValue(0).getValueType() == MVT::f32 ||
          N.getValue(0).getValueType() == MVT::f64)
        ))
-       && opcode != ISD::CALL
+      && opcode != ISD::CALL && opcode != ISD::TAILCALL
       )
     return SelectExprFP(N, Result);
 
@@ -1376,6 +1376,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
       .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
     return Result;
 
+  case ISD::TAILCALL:
   case ISD::CALL:
     {
       Select(N.getOperand(0));
@@ -2242,6 +2243,7 @@ void ISel::Select(SDOperand N) {
   case ISD::ZEXTLOAD:
   case ISD::LOAD:
   case ISD::CopyFromReg:
+  case ISD::TAILCALL:
   case ISD::CALL:
   case ISD::DYNAMIC_STACKALLOC:
     ExprMap.erase(N);
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index f4c50c09fa..3cd32ba697 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -953,7 +953,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
   unsigned &Reg = ExprMap[N];
   if (Reg) return Reg;
 
-  if (N.getOpcode() != ISD::CALL)
+  if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL)
     Reg = Result = (N.getValueType() != MVT::Other) ?
       MakeReg(N.getValueType()) : 1;
   else {
@@ -2072,6 +2072,7 @@ pC = pA OR pB
       return Result;
   }
 
+  case ISD::TAILCALL:
   case ISD::CALL: {
       Select(N.getOperand(0));
 
@@ -2342,6 +2343,7 @@ void ISel::Select(SDOperand N) {
   case ISD::ZEXTLOAD:
   case ISD::SEXTLOAD:
   case ISD::LOAD:
+  case ISD::TAILCALL:
   case ISD::CALL:
   case ISD::CopyFromReg:
   case ISD::DYNAMIC_STACKALLOC:
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index ce74c58d2e..41138cf7ef 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -939,6 +939,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     Reg = Result = (N.getValueType() != MVT::Other) ?
                             MakeReg(N.getValueType()) : 1;
     break;
+  case ISD::TAILCALL:
   case ISD::CALL:
     // If this is a call instruction, make sure to prepare ALL of the result
     // values as well as the chain.
@@ -1070,6 +1071,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
     return Result;
   }
 
+  case ISD::TAILCALL:
   case ISD::CALL: {
     unsigned GPR_idx = 0, FPR_idx = 0;
     static const unsigned GPR[] = {
@@ -1617,6 +1619,7 @@ void ISel::Select(SDOperand N) {
   case ISD::ZEXTLOAD:
   case ISD::LOAD:
   case ISD::CopyFromReg:
+  case ISD::TAILCALL:
   case ISD::CALL:
   case ISD::DYNAMIC_STACKALLOC:
     ExprMap.erase(N);
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 4eeaa24d2b..9150306d81 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1539,6 +1539,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Reg = Result = (N.getValueType() != MVT::Other) ?
                             MakeReg(N.getValueType()) : 1;
     break;
+  case ISD::TAILCALL:
   case ISD::CALL:
     // If this is a call instruction, make sure to prepare ALL of the result
     // values as well as the chain.
@@ -1569,7 +1570,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
   if (DestType == MVT::f64 || DestType == MVT::f32)
     if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
-        ISD::UNDEF != opcode && ISD::CALL != opcode)
+        ISD::UNDEF != opcode && ISD::CALL != opcode && ISD::TAILCALL != opcode)
       return SelectExprFP(N, Result);
 
   switch (opcode) {
@@ -1680,6 +1681,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     return Result;
   }
 
+  case ISD::TAILCALL:
   case ISD::CALL: {
     unsigned GPR_idx = 0, FPR_idx = 0;
     static const unsigned GPR[] = {
@@ -2504,6 +2506,7 @@ void ISel::Select(SDOperand N) {
   case ISD::ZEXTLOAD:
   case ISD::LOAD:
   case ISD::CopyFromReg:
+  case ISD::TAILCALL:
   case ISD::CALL:
   case ISD::DYNAMIC_STACKALLOC:
     ExprMap.erase(N);