diff options
| author | Jim Grosbach <grosbach@apple.com> | 2012-05-21 17:57:17 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-05-21 17:57:17 +0000 |
| commit | b551f0cc7882cd9cc9c3a3b2e4d35bc942a9cb44 (patch) | |
| tree | 58d79643dea660b9bae3b37e1aba0234fb3c19da | |
| parent | 4c8f909cdf221195f1d306033a4f843c5a7ee81a (diff) | |
Thumb2: RSB source register should be rGRP not GPRnopc.
t2RSB defined the operand correctly, but tRSBS didn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157200 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 3b73c1fd43..c309f84b58 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -668,16 +668,16 @@ let hasPostISelHook = 1, Defs = [CPSR] in { multiclass T2I_rbin_s_is<PatFrag opnode> { // shifted imm def ri : t2PseudoInst<(outs rGPR:$Rd), - (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p), + (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p), 4, IIC_iALUi, [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, - GPRnopc:$Rn))]>; + rGPR:$Rn))]>; // shifted register def rs : t2PseudoInst<(outs rGPR:$Rd), - (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p), + (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 4, IIC_iALUsi, [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, - GPRnopc:$Rn))]>; + rGPR:$Rn))]>; } } |