diff options
| author | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:17:09 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-21 15:17:09 +0000 |
| commit | b4dc10c8c5df75c0b281e0d815018b5830b965b9 (patch) | |
| tree | a5318c7f979817291ac56cb3e651f148d3eecab1 | |
| parent | 7b3dab2673128257b6bf9a3eaa4fe5aad9c9a675 (diff) | |
R600/SI: rework VOP3 classes
Order the classes and add asm operands.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175751 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.td | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 0808f24c21..05325db4d0 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -127,20 +127,6 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> { // Vector ALU classes //===----------------------------------------------------------------------===// -class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 < - op, (outs VReg_32:$dst), - (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, - i32imm:$src4, i32imm:$src5, i32imm:$src6), - opName, pattern ->; - -class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < - op, (outs VReg_64:$dst), - (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2, - i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), - opName, pattern ->; - multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src, string opName, list<dag> pattern> { @@ -224,6 +210,20 @@ multiclass VOPC_64 <bits<8> op, string opName, ValueType vt = untyped, PatLeaf cond = COND_NULL> : VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>; +class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 < + op, (outs VReg_32:$dst), + (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, + i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg), + opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern +>; + +class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 < + op, (outs VReg_64:$dst), + (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2, + i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg), + opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern +>; + //===----------------------------------------------------------------------===// // Vector I/O classes //===----------------------------------------------------------------------===// |