diff options
author | Chris Lattner <sabre@nondot.org> | 2007-05-17 18:15:41 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2007-05-17 18:15:41 +0000 |
commit | b429f7303eecc6fe0218d86e2f1321f70473deb4 (patch) | |
tree | ba705483a3e79311f991854be4e6d6239da26d2d | |
parent | 59807fabd751d6d2df9e4b49503e45f58d9277e5 (diff) |
add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37168 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 26ce7b9470..4abb68b2a7 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -5222,6 +5222,48 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ } break; } + + case ISD::ADDC: + case ISD::SUBC: { + // Expand the subcomponents. + SDOperand LHSL, LHSH, RHSL, RHSH; + ExpandOp(Node->getOperand(0), LHSL, LHSH); + ExpandOp(Node->getOperand(1), RHSL, RHSH); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); + SDOperand LoOps[2] = { LHSL, RHSL }; + SDOperand HiOps[3] = { LHSH, RHSH }; + + if (Node->getOpcode() == ISD::ADDC) { + Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); + HiOps[2] = Lo.getValue(1); + Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); + } else { + Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); + HiOps[2] = Lo.getValue(1); + Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); + } + // Remember that we legalized the flag. + AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); + break; + } + case ISD::ADDE: + case ISD::SUBE: { + // Expand the subcomponents. + SDOperand LHSL, LHSH, RHSL, RHSH; + ExpandOp(Node->getOperand(0), LHSL, LHSH); + ExpandOp(Node->getOperand(1), RHSL, RHSH); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); + SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; + SDOperand HiOps[3] = { LHSH, RHSH }; + + Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); + HiOps[2] = Lo.getValue(1); + Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); + + // Remember that we legalized the flag. + AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); + break; + } case ISD::MUL: { // If the target wants to custom expand this, let them. if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { |