Change the x86 assembly output to use tab characters to separate the

mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8

35 files changed, 1163 insertions, 1163 deletions

diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index 456cc7bd06..3b0cc16e39 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -165,9 +165,9 @@ def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW
                   [(set RFP64:$dst, 
                     (OpNode RFP64:$src1, (extloadf32 addr:$src2)))]>;
 def _F32m  : FPI<0xD8, fp, (outs), (ins f32mem:$src), 
-                 !strconcat("f", !strconcat(asmstring, "{s} $src"))>;
+                 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
 def _F64m  : FPI<0xDC, fp, (outs), (ins f64mem:$src), 
-                 !strconcat("f", !strconcat(asmstring, "{l} $src"))>;
+                 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
 // ST(0) = ST(0) + [memint]
 def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
                     [(set RFP32:$dst, (OpNode RFP32:$src1,
@@ -182,9 +182,9 @@ def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFP
                     [(set RFP64:$dst, (OpNode RFP64:$src1,
                                        (X86fild addr:$src2, i32)))]>;
 def _FI16m  : FPI<0xDE, fp, (outs), (ins i16mem:$src), 
-                  !strconcat("fi", !strconcat(asmstring, "{s} $src"))>;
+                  !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
 def _FI32m  : FPI<0xDA, fp, (outs), (ins i32mem:$src), 
-                  !strconcat("fi", !strconcat(asmstring, "{l} $src"))>;
+                  !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
 }
 
 defm ADD : FPBinary_rr<fadd>;
@@ -208,24 +208,24 @@ class FPrST0PInst<bits<8> o, string asm>
 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
 // of some of the 'reverse' forms of the fsub and fdiv instructions.  As such,
 // we have to put some 'r's in and take them out of weird places.
-def ADD_FST0r   : FPST0rInst <0xC0, "fadd $op">;
-def ADD_FrST0   : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
-def ADD_FPrST0  : FPrST0PInst<0xC0, "faddp $op">;
-def SUBR_FST0r  : FPST0rInst <0xE8, "fsubr $op">;
-def SUB_FrST0   : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
-def SUB_FPrST0  : FPrST0PInst<0xE8, "fsub{r}p $op">;
-def SUB_FST0r   : FPST0rInst <0xE0, "fsub $op">;
-def SUBR_FrST0  : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
-def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
-def MUL_FST0r   : FPST0rInst <0xC8, "fmul $op">;
-def MUL_FrST0   : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
-def MUL_FPrST0  : FPrST0PInst<0xC8, "fmulp $op">;
-def DIVR_FST0r  : FPST0rInst <0xF8, "fdivr $op">;
-def DIV_FrST0   : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
-def DIV_FPrST0  : FPrST0PInst<0xF8, "fdiv{r}p $op">;
-def DIV_FST0r   : FPST0rInst <0xF0, "fdiv $op">;
-def DIVR_FrST0  : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
-def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
+def ADD_FST0r   : FPST0rInst <0xC0, "fadd\t$op">;
+def ADD_FrST0   : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
+def ADD_FPrST0  : FPrST0PInst<0xC0, "faddp\t$op">;
+def SUBR_FST0r  : FPST0rInst <0xE8, "fsubr\t$op">;
+def SUB_FrST0   : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
+def SUB_FPrST0  : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
+def SUB_FST0r   : FPST0rInst <0xE0, "fsub\t$op">;
+def SUBR_FrST0  : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
+def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
+def MUL_FST0r   : FPST0rInst <0xC8, "fmul\t$op">;
+def MUL_FrST0   : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
+def MUL_FPrST0  : FPrST0PInst<0xC8, "fmulp\t$op">;
+def DIVR_FST0r  : FPST0rInst <0xF8, "fdivr\t$op">;
+def DIV_FrST0   : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
+def DIV_FPrST0  : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
+def DIV_FST0r   : FPST0rInst <0xF0, "fdiv\t$op">;
+def DIVR_FrST0  : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
+def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
 
 // Unary operations.
 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
@@ -270,21 +270,21 @@ defm CMOVNP : FPCMov<X86_COND_NP>;
 
 // These are not factored because there's no clean way to pass DA/DB.
 def CMOVB_F  : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
+                  "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
+                  "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
 def CMOVE_F  : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
+                  "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
 def CMOVP_F  : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovu  {$op, %st(0)|%ST(0), $op}">, DA;
+                  "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
+                  "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
+                  "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
+                  "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
-                  "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
+                  "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
 
 // Floating point loads & stores.
 def LD_Fp32m   : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
@@ -321,20 +321,20 @@ def IST_Fp16m64  : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
 def IST_Fp32m64  : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
 def IST_Fp64m64  : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
 
-def LD_F32m   : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s} $src">;
-def LD_F64m   : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l} $src">;
-def ILD_F16m  : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s} $src">;
-def ILD_F32m  : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l} $src">;
-def ILD_F64m  : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll} $src">;
-def ST_F32m   : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s} $dst">;
-def ST_F64m   : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l} $dst">;
-def ST_FP32m  : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s} $dst">;
-def ST_FP64m  : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l} $dst">;
-def IST_F16m  : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s} $dst">;
-def IST_F32m  : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l} $dst">;
-def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s} $dst">;
-def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l} $dst">;
-def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll} $dst">;
+def LD_F32m   : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
+def LD_F64m   : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
+def ILD_F16m  : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
+def ILD_F32m  : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
+def ILD_F64m  : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
+def ST_F32m   : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
+def ST_F64m   : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
+def ST_FP32m  : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
+def ST_FP64m  : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
+def IST_F16m  : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
+def IST_F32m  : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
+def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
+def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
+def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
 
 // FISTTP requires SSE3 even though it's a FPStack op.
 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
@@ -356,15 +356,15 @@ def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
                     [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
                     Requires<[HasSSE3]>;
 
-def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s} $dst">;
-def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l} $dst">;
-def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll} $dst">;
+def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
+def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
+def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
 
 // FP Stack manipulation instructions.
-def LD_Frr   : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld $op">, D9;
-def ST_Frr   : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst $op">, DD;
-def ST_FPrr  : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp $op">, DD;
-def XCH_F    : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch $op">, D9;
+def LD_Frr   : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
+def ST_Frr   : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
+def ST_FPrr  : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
+def XCH_F    : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
 
 // Floating point constant loads.
 let isReMaterializable = 1 in {
@@ -394,29 +394,29 @@ def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
 
 def UCOM_Fr    : FPI<0xE0, AddRegFrm,    // FPSW = cmp ST(0) with ST(i)
                     (outs), (ins RST:$reg),
-                    "fucom $reg">, DD, Imp<[ST0],[]>;
+                    "fucom\t$reg">, DD, Imp<[ST0],[]>;
 def UCOM_FPr   : FPI<0xE8, AddRegFrm,    // FPSW = cmp ST(0) with ST(i), pop
                     (outs), (ins RST:$reg),
-                    "fucomp $reg">, DD, Imp<[ST0],[]>;
+                    "fucomp\t$reg">, DD, Imp<[ST0],[]>;
 def UCOM_FPPr  : FPI<0xE9, RawFrm,       // cmp ST(0) with ST(1), pop, pop
                     (outs), (ins),
                     "fucompp">, DA, Imp<[ST0],[]>;
 
 def UCOM_FIr   : FPI<0xE8, AddRegFrm,     // CC = cmp ST(0) with ST(i)
                     (outs), (ins RST:$reg),
-                    "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
+                    "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
 def UCOM_FIPr  : FPI<0xE8, AddRegFrm,     // CC = cmp ST(0) with ST(i), pop
                     (outs), (ins RST:$reg),
-                    "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
+                    "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
 
 // Floating point flag ops.
 def FNSTSW8r  : I<0xE0, RawFrm,                  // AX = fp flags
                   (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
 
 def FNSTCW16m : I<0xD9, MRM7m,                   // [mem16] = X87 control world
-                  (outs), (ins i16mem:$dst), "fnstcw $dst", []>;
+                  (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
 def FLDCW16m  : I<0xD9, MRM5m,                   // X87 control world = [mem16]
-                  (outs), (ins i16mem:$dst), "fldcw $dst", []>;
+                  (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index de292c9cad..217f6d5195 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -275,7 +275,7 @@ def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
 let isTerminator = 1, isReturn = 1, isBarrier = 1,
     hasCtrlDep = 1 in {
   def RET    : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
-  def RETI   : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret $amt",
+  def RETI   : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
                     [(X86retflag imm:$amt)]>;
 }
 
@@ -286,49 +286,49 @@ let isBranch = 1, isTerminator = 1 in
 
 // Indirect branches
 let isBranch = 1, isBarrier = 1 in
-  def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
+  def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
-  def JMP32r     : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l} {*}$dst",
+  def JMP32r     : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
                      [(brind GR32:$dst)]>;
-  def JMP32m     : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l} {*}$dst",
+  def JMP32m     : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
                      [(brind (loadi32 addr:$dst))]>;
 }
 
 // Conditional branches
-def JE  : IBr<0x84, (ins brtarget:$dst), "je $dst",
+def JE  : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
               [(X86brcond bb:$dst, X86_COND_E)]>, TB;
-def JNE : IBr<0x85, (ins brtarget:$dst), "jne $dst",
+def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
               [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
-def JL  : IBr<0x8C, (ins brtarget:$dst), "jl $dst",
+def JL  : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
               [(X86brcond bb:$dst, X86_COND_L)]>, TB;
-def JLE : IBr<0x8E, (ins brtarget:$dst), "jle $dst",
+def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
               [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
-def JG  : IBr<0x8F, (ins brtarget:$dst), "jg $dst",
+def JG  : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
               [(X86brcond bb:$dst, X86_COND_G)]>, TB;
-def JGE : IBr<0x8D, (ins brtarget:$dst), "jge $dst",
+def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
               [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
 
-def JB  : IBr<0x82, (ins brtarget:$dst), "jb $dst",
+def JB  : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
               [(X86brcond bb:$dst, X86_COND_B)]>, TB;
-def JBE : IBr<0x86, (ins brtarget:$dst), "jbe $dst",
+def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
               [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
-def JA  : IBr<0x87, (ins brtarget:$dst), "ja $dst",
+def JA  : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
               [(X86brcond bb:$dst, X86_COND_A)]>, TB;
-def JAE : IBr<0x83, (ins brtarget:$dst), "jae $dst",
+def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
               [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
 
-def JS  : IBr<0x88, (ins brtarget:$dst), "js $dst",
+def JS  : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
               [(X86brcond bb:$dst, X86_COND_S)]>, TB;
-def JNS : IBr<0x89, (ins brtarget:$dst), "jns $dst",
+def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
               [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
-def JP  : IBr<0x8A, (ins brtarget:$dst), "jp $dst",
+def JP  : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
               [(X86brcond bb:$dst, X86_COND_P)]>, TB;
-def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp $dst",
+def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
               [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
-def JO  : IBr<0x80, (ins brtarget:$dst), "jo $dst",
+def JO  : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
               [(X86brcond bb:$dst, X86_COND_O)]>, TB;
-def JNO : IBr<0x81, (ins brtarget:$dst), "jno $dst",
+def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
               [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
 
 //===----------------------------------------------------------------------===//
@@ -340,23 +340,23 @@ let isCall = 1 in
               MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
               XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
     def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops),
-                        "call ${dst:call}", []>;
+                        "call\t${dst:call}", []>;
     def CALL32r     : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
-                        "call {*}$dst", [(X86call GR32:$dst)]>;
+                        "call\t{*}$dst", [(X86call GR32:$dst)]>;
     def CALL32m     : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
-                        "call {*}$dst", []>;
+                        "call\t{*}$dst", []>;
   }
 
 // Tail call stuff.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp ${dst:call}  # TAIL CALL",
+  def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call}  # TAIL CALL",
                  []>;
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
-  def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp {*}$dst  # TAIL CALL",
+  def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp\t{*}$dst  # TAIL CALL",
                  []>;
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
   def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
-                   "jmp {*}$dst  # TAIL CALL", []>;
+                   "jmp\t{*}$dst  # TAIL CALL", []>;
 
 //===----------------------------------------------------------------------===//
 //  Miscellaneous Instructions...
@@ -364,56 +364,56 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
 def LEAVE    : I<0xC9, RawFrm,
                  (outs), (ins), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
 def POP32r   : I<0x58, AddRegFrm,
-                 (outs GR32:$reg), (ins), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
+                 (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, Imp<[ESP],[ESP]>;
 
 def PUSH32r  : I<0x50, AddRegFrm,
-                 (outs), (ins GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>;
+                 (outs), (ins GR32:$reg), "push{l}\t$reg", []>, Imp<[ESP],[ESP]>;
 
 def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
-                      "call $label", []>;
+                      "call\t$label", []>;
 
 let isTwoAddress = 1 in                               // GR32 = bswap GR32
   def BSWAP32r : I<0xC8, AddRegFrm,
                    (outs GR32:$dst), (ins GR32:$src),
-                   "bswap{l} $dst", 
+                   "bswap{l}\t$dst", 
                    [(set GR32:$dst, (bswap GR32:$src))]>, TB;
 
 // FIXME: Model xchg* as two address instructions?
 def XCHG8rr  : I<0x86, MRMDestReg,                    // xchg GR8, GR8
                  (outs), (ins GR8:$src1, GR8:$src2),
-                 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
+                 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
 def XCHG16rr : I<0x87, MRMDestReg,                    // xchg GR16, GR16
                  (outs), (ins GR16:$src1, GR16:$src2),
-                 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
+                 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
 def XCHG32rr : I<0x87, MRMDestReg,                    // xchg GR32, GR32
                  (outs), (ins GR32:$src1, GR32:$src2),
-                 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
+                 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
 
 def XCHG8mr  : I<0x86, MRMDestMem,
                  (outs), (ins i8mem:$src1, GR8:$src2),
-                 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
+                 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
 def XCHG16mr : I<0x87, MRMDestMem,
                  (outs), (ins i16mem:$src1, GR16:$src2),
-                 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
+                 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
 def XCHG32mr : I<0x87, MRMDestMem,
                  (outs), (ins i32mem:$src1, GR32:$src2),
-                 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
+                 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
 def XCHG8rm  : I<0x86, MRMSrcMem,
                  (outs), (ins GR8:$src1, i8mem:$src2),
-                 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
+                 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
 def XCHG16rm : I<0x87, MRMSrcMem,
                  (outs), (ins GR16:$src1, i16mem:$src2),
-                 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
+                 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
 def XCHG32rm : I<0x87, MRMSrcMem,
                  (outs), (ins GR32:$src1, i32mem:$src2),
-                 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
+                 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
 
 def LEA16r   : I<0x8D, MRMSrcMem,
                  (outs GR16:$dst), (ins i32mem:$src),
-                 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
+                 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
 def LEA32r   : I<0x8D, MRMSrcMem,
                  (outs GR32:$dst), (ins lea32mem:$src),
-                 "lea{l} {$src|$dst}, {$dst|$src}",
+                 "lea{l}\t{$src|$dst}, {$dst|$src}",
                  [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
 
 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
@@ -443,48 +443,48 @@ def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
 //  Input/Output Instructions...
 //
 def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
-               "in{b} {%dx, %al|%AL, %DX}",
+               "in{b}\t{%dx, %al|%AL, %DX}",
                []>,  Imp<[DX], [AL]>;
 def IN16rr : I<0xED, RawFrm, (outs), (ins),
-               "in{w} {%dx, %ax|%AX, %DX}",
+               "in{w}\t{%dx, %ax|%AX, %DX}",
                []>,  Imp<[DX], [AX]>, OpSize;
 def IN32rr : I<0xED, RawFrm, (outs), (ins),
-               "in{l} {%dx, %eax|%EAX, %DX}",
+               "in{l}\t{%dx, %eax|%EAX, %DX}",
                []>, Imp<[DX],[EAX]>;
 
 def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
-                  "in{b} {$port, %al|%AL, $port}",
+                  "in{b}\t{$port, %al|%AL, $port}",
                  []>,
              Imp<[], [AL]>;
 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
-                  "in{w} {$port, %ax|%AX, $port}",
+                  "in{w}\t{$port, %ax|%AX, $port}",
                  []>,
              Imp<[], [AX]>, OpSize;
 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
-                  "in{l} {$port, %eax|%EAX, $port}",
+                  "in{l}\t{$port, %eax|%EAX, $port}",
                  []>,
              Imp<[],[EAX]>;
 
 def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
-                "out{b} {%al, %dx|%DX, %AL}",
+                "out{b}\t{%al, %dx|%DX, %AL}",
                 []>,  Imp<[DX,  AL], []>;
 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
-                "out{w} {%ax, %dx|%DX, %AX}",
+                "out{w}\t{%ax, %dx|%DX, %AX}",
                 []>,  Imp<[DX,  AX], []>, OpSize;
 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
-                "out{l} {%eax, %dx|%DX, %EAX}",
+                "out{l}\t{%eax, %dx|%DX, %EAX}",
                 []>, Imp<[DX, EAX], []>;
 
 def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
-                   "out{b} {%al, $port|$port, %AL}",
+                   "out{b}\t{%al, $port|$port, %AL}",
                    []>,
               Imp<[AL], []>;
 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
-                   "out{w} {%ax, $port|$port, %AX}",
+                   "out{w}\t{%ax, $port|$port, %AX}",
                    []>,
               Imp<[AX], []>, OpSize;
 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
-                   "out{l} {%eax, $port|$port, %EAX}",
+                   "out{l}\t{%eax, $port|$port, %EAX}",
                    []>,
               Imp<[EAX], []>;
 
@@ -492,50 +492,50 @@ def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
 //  Move Instructions...
 //
 def MOV8rr  : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
-                "mov{b} {$src, $dst|$dst, $src}", []>;
+                "mov{b}\t{$src, $dst|$dst, $src}", []>;
 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
-                "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
+                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
-                "mov{l} {$src, $dst|$dst, $src}", []>;
+                "mov{l}\t{$src, $dst|$dst, $src}", []>;
 let isReMaterializable = 1 in {
 def MOV8ri  : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
-                   "mov{b} {$src, $dst|$dst, $src}",
+                   "mov{b}\t{$src, $dst|$dst, $src}",
                    [(set GR8:$dst, imm:$src)]>;
 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
-                   "mov{w} {$src, $dst|$dst, $src}",
+                   "mov{w}\t{$src, $dst|$dst, $src}",
                    [(set GR16:$dst, imm:$src)]>, OpSize;
 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
-                   "mov{l} {$src, $dst|$dst, $src}",
+                   "mov{l}\t{$src, $dst|$dst, $src}",
                    [(set GR32:$dst, imm:$src)]>;
 }
 def MOV8mi  : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
-                   "mov{b} {$src, $dst|$dst, $src}",
+                   "mov{b}\t{$src, $dst|$dst, $src}",
                    [(store (i8 imm:$src), addr:$dst)]>;
 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
-                   "mov{w} {$src, $dst|$dst, $src}",
+                   "mov{w}\t{$src, $dst|$dst, $src}",
                    [(store (i16 imm:$src), addr:$dst)]>, OpSize;
 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
-                   "mov{l} {$src, $dst|$dst, $src}",
+                   "mov{l}\t{$src, $dst|$dst, $src}",
                    [(store (i32 imm:$src), addr:$dst)]>;
 
 def MOV8rm  : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
-                "mov{b} {$src, $dst|$dst, $src}",
+                "mov{b}\t{$src, $dst|$dst, $src}",
                 [(set GR8:$dst, (load addr:$src))]>;
 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
-                "mov{w} {$src, $dst|$dst, $src}",
+                "mov{w}\t{$src, $dst|$dst, $src}",
                 [(set GR16:$dst, (load addr:$src))]>, OpSize;
 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
-                "mov{l} {$src, $dst|$dst, $src}",
+                "mov{l}\t{$src, $dst|$dst, $src}",
                 [(set GR32:$dst, (load addr:$src))]>;
 
 def MOV8mr  : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
-                "mov{b} {$src, $dst|$dst, $src}",
+                "mov{b}\t{$src, $dst|$dst, $src}",
                 [(store GR8:$src, addr:$dst)]>;
 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
-                "mov{w} {$src, $dst|$dst, $src}",
+                "mov{w}\t{$src, $dst|$dst, $src}",
                 [(store GR16:$src, addr:$dst)]>, OpSize;
 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
-                "mov{l} {$src, $dst|$dst, $src}",
+                "mov{l}\t{$src, $dst|$dst, $src}",
                 [(store GR32:$src, addr:$dst)]>;
                 
 //===----------------------------------------------------------------------===//
@@ -543,71 +543,71 @@ def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
 //
 
 // Extra precision multiplication
-def MUL8r  : I<0xF6, MRM4r, (outs),  (ins GR8:$src), "mul{b} $src",
+def MUL8r  : I<0xF6, MRM4r, (outs),  (ins GR8:$src), "mul{b}\t$src",
                // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
                // This probably ought to be moved to a def : Pat<> if the
                // syntax can be accepted.
                [(set AL, (mul AL, GR8:$src))]>,
              Imp<[AL],[AX]>;               // AL,AH = AL*GR8
-def MUL16r : I<0xF7, MRM4r, (outs),  (ins GR16:$src), "mul{w} $src", []>,
+def MUL16r : I<0xF7, MRM4r, (outs),  (ins GR16:$src), "mul{w}\t$src", []>,
              Imp<[AX],[AX,DX]>, OpSize;    // AX,DX = AX*GR16
-def MUL32r : I<0xF7, MRM4r, (outs),  (ins GR32:$src), "mul{l} $src", []>,
+def MUL32r : I<0xF7, MRM4r, (outs),  (ins GR32:$src), "mul{l}\t$src", []>,
              Imp<[EAX],[EAX,EDX]>;         // EAX,EDX = EAX*GR32
 def MUL8m  : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
-               "mul{b} $src",
+               "mul{b}\t$src",
                // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
                // This probably ought to be moved to a def : Pat<> if the
                // syntax can be accepted.
                [(set AL, (mul AL, (loadi8 addr:$src)))]>,
              Imp<[AL],[AX]>;          // AL,AH = AL*[mem8]
 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
-               "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
+               "mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
                OpSize; // AX,DX = AX*[mem16]
 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
-               "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
+               "mul{l}\t$src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
 
-def IMUL8r  : I<0xF6, MRM5r, (outs),  (ins GR8:$src), "imul{b} $src", []>,
+def IMUL8r  : I<0xF6, MRM5r, (outs),  (ins GR8:$src), "imul{b}\t$src", []>,