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authorEvan Cheng <evan.cheng@apple.com>2006-10-11 21:03:53 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-10-11 21:03:53 +0000
commitaf9db75943c11eebd642c1645d3c3f4003fe37e3 (patch)
tree070aea442199e4facfd16b484c74296479168ce4
parent94b3040fef9475c74b877fb32cb45200cea273bb (diff)
Add properties to ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td7
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td8
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.td4
-rw-r--r--lib/Target/TargetSelectionDAG.td4
-rw-r--r--lib/Target/X86/X86InstrInfo.td4
-rw-r--r--lib/Target/X86/X86InstrX86-64.td2
6 files changed, 16 insertions, 13 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3281e975bc..9873e44eb8 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -27,12 +27,13 @@ def memri : Operand<iPTR> {
// Define ARM specific addressing mode.
//Addressing Mode 1: data processing operands
-def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl]>;
+def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
+ []>;
//register plus/minus 12 bit offset
-def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
+def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
//register plus scaled register
-//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
+//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
//===----------------------------------------------------------------------===//
// Instructions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index f346717a3d..b044d77db8 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -259,10 +259,10 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
}
// Define PowerPC specific addressing mode.
-def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
-def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
-def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
-def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
+def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
+def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
+def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
+def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 6fc4481934..713f0e52d9 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -67,8 +67,8 @@ def SETHIimm : PatLeaf<(imm), [{
}], HI22>;
// Addressing modes.
-def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
-def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
+def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
+def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
// Address operands
def MEMrr : Operand<i32> {
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index bd2b2e576c..778212eced 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -554,11 +554,13 @@ class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
// RootNodes are the list of possible root nodes of the sub-dags to match.
// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
//
-class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = []> {
+class ComplexPattern<ValueType ty, int numops, string fn,
+ list<SDNode> roots = [], list<SDNodeProperty> props = []> {
ValueType Ty = ty;
int NumOperands = numops;
string SelectFunc = fn;
list<SDNode> RootNodes = roots;
+ list<SDNodeProperty> Properties = props;
}
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 27c8434179..11c67bff06 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -135,9 +135,9 @@ def brtarget : Operand<OtherVT>;
//
// Define X86 specific addressing mode.
-def addr : ComplexPattern<iPTR, 4, "SelectAddr", []>;
+def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
- [add, mul, shl, or, frameindex]>;
+ [add, mul, shl, or, frameindex], []>;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.
diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index db060e6151..cd6ac5e03a 100644
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -38,7 +38,7 @@ def lea64_32mem : Operand<i32> {
// Complex Pattern Definitions...
//
def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
- [add, mul, shl, or, frameindex, X86Wrapper]>;
+ [add, mul, shl, or, frameindex, X86Wrapper], []>;
//===----------------------------------------------------------------------===//
// Instruction templates...