diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-01-12 18:57:33 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-01-12 18:57:33 +0000 |
| commit | af551bcf6be6c2c44b1b5dac5573c58bdc3da972 (patch) | |
| tree | 8341716a6f3cbdc2b012a3d1a28a43d7f8a4eedb | |
| parent | 4bb91024ac2dcdff363488617ffcfb3b5c99fc49 (diff) | |
Don't create rotate instructions in unsupported types, because we don't have
promote/expand code yet. This fixes the 177.mesa failure on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25250 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1d356689fb..cb80e25038 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1184,7 +1184,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { // check for rotl, rotr if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && N0.getOperand(0) == N1.getOperand(0) && - TLI.isOperationLegal(ISD::ROTL, VT)) { + TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) if (N0.getOperand(1).getOpcode() == ISD::Constant && N1.getOperand(1).getOpcode() == ISD::Constant) { @@ -1206,7 +1206,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) if (SUBC->getValue() == OpSizeInBits) { - if (TLI.isOperationLegal(ISD::ROTR, VT)) + if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), N1.getOperand(1)); else |