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| author | Johnny Chen <johnny.chen@apple.com> | 2010-01-25 22:54:29 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-01-25 22:54:29 +0000 |
| commit | aeb326aad70acd1dd8b08564be4165eabc9ef542 (patch) | |
| tree | d0f1b9787189391ffe9f0b4e83f9e5eeeb5e4682 | |
| parent | 44e87255e9b7a9d8ecb558690db1181882c08045 (diff) | |
Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index e4b18088ad..0d4200c63d 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -124,7 +124,7 @@ def FPSCR : ARMReg<1, "fpscr">; // def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, - LR, SP, PC]> { + SP, LR, PC]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; iterator allocation_order_end(const MachineFunction &MF) const; |