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authorRafael Espindola <rafael.espindola@gmail.com>2006-10-09 14:13:40 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-10-09 14:13:40 +0000
commitad557f9d11b942efe858a27e330a15d9f0af5dad (patch)
tree657462b6128d62315fb50fbfc421114d385ecce1
parent896f10c30995dd522eadea553780785d8cf967d6 (diff)
expand ISD::EXTLOAD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30827 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 3f3b949464..9c64445d39 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -47,6 +47,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass);
addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass);
+ setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);