diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-17 10:15:22 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-17 10:15:22 +0000 |
| commit | aceb620de855485a4fb2eed343d880d76f6c701c (patch) | |
| tree | a83f5ebb8a6e4006b73ac8f12f2c697b7454c669 | |
| parent | 48839d9973f8f327bbd07babf62ac67f37010014 (diff) | |
Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71975 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/MSP430/MSP430ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/MSP430/MSP430InstrInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/MSP430/2009-05-17-Shift.ll | 15 |
3 files changed, 18 insertions, 3 deletions
diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index 181658665d..387cebffc0 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -468,7 +468,7 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op, } while (ShiftAmount--) - Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA), + Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), dl, VT, Victim); return Victim; diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index de1b2ad648..39c08e40be 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -624,12 +624,12 @@ def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src), (implicit SRW)]>; def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src), - "clrc\n" + "clrc\n\t" "rrc.b\t$dst", [(set GR8:$dst, (MSP430rrc GR8:$src)), (implicit SRW)]>; def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src), - "clrc\n" + "clrc\n\t" "rrc.w\t$dst", [(set GR16:$dst, (MSP430rrc GR16:$src)), (implicit SRW)]>; diff --git a/test/CodeGen/MSP430/2009-05-17-Shift.ll b/test/CodeGen/MSP430/2009-05-17-Shift.ll new file mode 100644 index 0000000000..b048bb3fd3 --- /dev/null +++ b/test/CodeGen/MSP430/2009-05-17-Shift.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=msp430 | grep rra | count 1 + +define i16 @lsr2u16(i16 %x.arg) nounwind { + %retval = alloca i16 + %x = alloca i16 + store i16 %x.arg, i16* %x + %1 = load i16* %x + %2 = lshr i16 %1, 2 + store i16 %2, i16* %retval + br label %return +return: + %3 = load i16* %retval + ret i16 %3 + +}
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